2 * linux/arch/arm/mach-omap1/clock.h
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
14 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
16 static int omap1_clk_enable_generic(struct clk * clk);
17 static void omap1_clk_disable_generic(struct clk * clk);
18 static void omap1_ckctl_recalc(struct clk * clk);
19 static void omap1_watchdog_recalc(struct clk * clk);
20 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
21 static void omap1_sossi_recalc(struct clk *clk);
22 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk);
23 static int omap1_clk_enable_dsp_domain(struct clk * clk);
24 static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
25 static void omap1_clk_disable_dsp_domain(struct clk * clk);
26 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
27 static void omap1_uart_recalc(struct clk * clk);
28 static int omap1_clk_enable_uart_functional(struct clk * clk);
29 static void omap1_clk_disable_uart_functional(struct clk * clk);
30 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
31 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
32 static void omap1_init_ext_clk(struct clk * clk);
33 static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
34 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
35 static int omap1_clk_enable(struct clk *clk);
36 static void omap1_clk_disable(struct clk *clk);
41 unsigned long pll_rate;
48 unsigned long sysc_addr;
51 /* Provide a method for preventing idling some ARM IDLECT clocks */
52 struct arm_idlect1_clk {
54 unsigned long no_idle_count;
58 /* ARM_CKCTL bit shifts */
59 #define CKCTL_PERDIV_OFFSET 0
60 #define CKCTL_LCDDIV_OFFSET 2
61 #define CKCTL_ARMDIV_OFFSET 4
62 #define CKCTL_DSPDIV_OFFSET 6
63 #define CKCTL_TCDIV_OFFSET 8
64 #define CKCTL_DSPMMUDIV_OFFSET 10
65 /*#define ARM_TIMXO 12*/
67 /*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */
68 /* DSP_CKCTL bit shifts */
69 #define CKCTL_DSPPERDIV_OFFSET 0
71 /* ARM_IDLECT2 bit shifts */
76 #define EN_LBCK 4 /* Not on 1610/1710 */
77 /*#define EN_HSABCK 5*/
81 #define EN_GPIOCK 9 /* Not on 1610/1710 */
82 /*#define EN_LBFREECK 10*/
83 #define EN_CKOUT_ARM 11
85 /* ARM_IDLECT3 bit shifts */
90 /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
93 /* Various register defines for clock controls scattered around OMAP chip */
94 #define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */
95 #define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */
96 #define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */
97 #define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
98 #define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */
99 #define SWD_CLK_DIV_CTRL_SEL 0xfffe0874
100 #define COM_CLK_DIV_CTRL_SEL 0xfffe0878
101 #define SOFT_REQ_REG 0xfffe0834
102 #define SOFT_REQ_REG2 0xfffe0880
104 /*-------------------------------------------------------------------------
105 * Omap1 MPU rate table
106 *-------------------------------------------------------------------------*/
107 static struct mpu_rate rate_table[] = {
108 /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
109 * NOTE: Comment order here is different from bits in CKCTL value:
110 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
112 #if defined(CONFIG_OMAP_ARM_216MHZ)
113 { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
115 #if defined(CONFIG_OMAP_ARM_195MHZ)
116 { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
118 #if defined(CONFIG_OMAP_ARM_192MHZ)
119 { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
120 { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
121 { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
122 { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
123 { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
125 #if defined(CONFIG_OMAP_ARM_182MHZ)
126 { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
128 #if defined(CONFIG_OMAP_ARM_168MHZ)
129 { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
131 #if defined(CONFIG_OMAP_ARM_150MHZ)
132 { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
134 #if defined(CONFIG_OMAP_ARM_120MHZ)
135 { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
137 #if defined(CONFIG_OMAP_ARM_96MHZ)
138 { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
140 #if defined(CONFIG_OMAP_ARM_60MHZ)
141 { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
143 #if defined(CONFIG_OMAP_ARM_30MHZ)
144 { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
149 /*-------------------------------------------------------------------------
151 *-------------------------------------------------------------------------*/
153 static struct clk ck_ref = {
156 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
157 CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
158 .enable = &omap1_clk_enable_generic,
159 .disable = &omap1_clk_disable_generic,
162 static struct clk ck_dpll1 = {
165 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
166 CLOCK_IN_OMAP310 | RATE_PROPAGATES | ALWAYS_ENABLED,
167 .enable = &omap1_clk_enable_generic,
168 .disable = &omap1_clk_disable_generic,
171 static struct arm_idlect1_clk ck_dpll1out = {
173 .name = "ck_dpll1out",
175 .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL |
176 ENABLE_REG_32BIT | RATE_PROPAGATES,
177 .enable_reg = (void __iomem *)ARM_IDLECT2,
178 .enable_bit = EN_CKOUT_ARM,
179 .recalc = &followparent_recalc,
180 .enable = &omap1_clk_enable_generic,
181 .disable = &omap1_clk_disable_generic,
186 static struct clk sossi_ck = {
188 .parent = &ck_dpll1out.clk,
189 .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |
191 .enable_reg = (void __iomem *)MOD_CONF_CTRL_1,
193 .recalc = &omap1_sossi_recalc,
194 .set_rate = &omap1_set_sossi_rate,
195 .enable = &omap1_clk_enable_generic,
196 .disable = &omap1_clk_disable_generic,
199 static struct clk arm_ck = {
202 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
203 CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES |
205 .rate_offset = CKCTL_ARMDIV_OFFSET,
206 .recalc = &omap1_ckctl_recalc,
207 .enable = &omap1_clk_enable_generic,
208 .disable = &omap1_clk_disable_generic,
211 static struct arm_idlect1_clk armper_ck = {
215 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
216 CLOCK_IN_OMAP310 | RATE_CKCTL |
218 .enable_reg = (void __iomem *)ARM_IDLECT2,
219 .enable_bit = EN_PERCK,
220 .rate_offset = CKCTL_PERDIV_OFFSET,
221 .recalc = &omap1_ckctl_recalc,
222 .enable = &omap1_clk_enable_generic,
223 .disable = &omap1_clk_disable_generic,
228 static struct clk arm_gpio_ck = {
229 .name = "arm_gpio_ck",
231 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
232 .enable_reg = (void __iomem *)ARM_IDLECT2,
233 .enable_bit = EN_GPIOCK,
234 .recalc = &followparent_recalc,
235 .enable = &omap1_clk_enable_generic,
236 .disable = &omap1_clk_disable_generic,
239 static struct arm_idlect1_clk armxor_ck = {
243 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
244 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
245 .enable_reg = (void __iomem *)ARM_IDLECT2,
246 .enable_bit = EN_XORPCK,
247 .recalc = &followparent_recalc,
248 .enable = &omap1_clk_enable_generic,
249 .disable = &omap1_clk_disable_generic,
254 static struct arm_idlect1_clk armtim_ck = {
258 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
259 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
260 .enable_reg = (void __iomem *)ARM_IDLECT2,
261 .enable_bit = EN_TIMCK,
262 .recalc = &followparent_recalc,
263 .enable = &omap1_clk_enable_generic,
264 .disable = &omap1_clk_disable_generic,
269 static struct arm_idlect1_clk armwdt_ck = {
273 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
274 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
275 .enable_reg = (void __iomem *)ARM_IDLECT2,
276 .enable_bit = EN_WDTCK,
277 .recalc = &omap1_watchdog_recalc,
278 .enable = &omap1_clk_enable_generic,
279 .disable = &omap1_clk_disable_generic,
284 static struct clk arminth_ck16xx = {
285 .name = "arminth_ck",
287 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
288 .recalc = &followparent_recalc,
289 /* Note: On 16xx the frequency can be divided by 2 by programming
290 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
292 * 1510 version is in TC clocks.
294 .enable = &omap1_clk_enable_generic,
295 .disable = &omap1_clk_disable_generic,
298 static struct clk dsp_ck = {
301 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
303 .enable_reg = (void __iomem *)ARM_CKCTL,
304 .enable_bit = EN_DSPCK,
305 .rate_offset = CKCTL_DSPDIV_OFFSET,
306 .recalc = &omap1_ckctl_recalc,
307 .enable = &omap1_clk_enable_generic,
308 .disable = &omap1_clk_disable_generic,
311 static struct clk dspmmu_ck = {
314 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
315 RATE_CKCTL | ALWAYS_ENABLED,
316 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
317 .recalc = &omap1_ckctl_recalc,
318 .enable = &omap1_clk_enable_generic,
319 .disable = &omap1_clk_disable_generic,
322 static struct clk dspper_ck = {
325 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
326 RATE_CKCTL | VIRTUAL_IO_ADDRESS,
327 .enable_reg = DSP_IDLECT2,
328 .enable_bit = EN_PERCK,
329 .rate_offset = CKCTL_PERDIV_OFFSET,
330 .recalc = &omap1_ckctl_recalc_dsp_domain,
331 .set_rate = &omap1_clk_set_rate_dsp_domain,
332 .enable = &omap1_clk_enable_dsp_domain,
333 .disable = &omap1_clk_disable_dsp_domain,
336 static struct clk dspxor_ck = {
339 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
341 .enable_reg = DSP_IDLECT2,
342 .enable_bit = EN_XORPCK,
343 .recalc = &followparent_recalc,
344 .enable = &omap1_clk_enable_dsp_domain,
345 .disable = &omap1_clk_disable_dsp_domain,
348 static struct clk dsptim_ck = {
351 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
353 .enable_reg = DSP_IDLECT2,
354 .enable_bit = EN_DSPTIMCK,
355 .recalc = &followparent_recalc,
356 .enable = &omap1_clk_enable_dsp_domain,
357 .disable = &omap1_clk_disable_dsp_domain,
360 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
361 static struct arm_idlect1_clk tc_ck = {
365 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
366 CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
367 RATE_CKCTL | RATE_PROPAGATES |
368 ALWAYS_ENABLED | CLOCK_IDLE_CONTROL,
369 .rate_offset = CKCTL_TCDIV_OFFSET,
370 .recalc = &omap1_ckctl_recalc,
371 .enable = &omap1_clk_enable_generic,
372 .disable = &omap1_clk_disable_generic,
377 static struct clk arminth_ck1510 = {
378 .name = "arminth_ck",
379 .parent = &tc_ck.clk,
380 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
382 .recalc = &followparent_recalc,
383 /* Note: On 1510 the frequency follows TC_CK
385 * 16xx version is in MPU clocks.
387 .enable = &omap1_clk_enable_generic,
388 .disable = &omap1_clk_disable_generic,
391 static struct clk tipb_ck = {
392 /* No-idle controlled by "tc_ck" */
394 .parent = &tc_ck.clk,
395 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
397 .recalc = &followparent_recalc,
398 .enable = &omap1_clk_enable_generic,
399 .disable = &omap1_clk_disable_generic,
402 static struct clk l3_ocpi_ck = {
403 /* No-idle controlled by "tc_ck" */
404 .name = "l3_ocpi_ck",
405 .parent = &tc_ck.clk,
406 .flags = CLOCK_IN_OMAP16XX,
407 .enable_reg = (void __iomem *)ARM_IDLECT3,
408 .enable_bit = EN_OCPI_CK,
409 .recalc = &followparent_recalc,
410 .enable = &omap1_clk_enable_generic,
411 .disable = &omap1_clk_disable_generic,
414 static struct clk tc1_ck = {
416 .parent = &tc_ck.clk,
417 .flags = CLOCK_IN_OMAP16XX,
418 .enable_reg = (void __iomem *)ARM_IDLECT3,
419 .enable_bit = EN_TC1_CK,
420 .recalc = &followparent_recalc,
421 .enable = &omap1_clk_enable_generic,
422 .disable = &omap1_clk_disable_generic,
425 static struct clk tc2_ck = {
427 .parent = &tc_ck.clk,
428 .flags = CLOCK_IN_OMAP16XX,
429 .enable_reg = (void __iomem *)ARM_IDLECT3,
430 .enable_bit = EN_TC2_CK,
431 .recalc = &followparent_recalc,
432 .enable = &omap1_clk_enable_generic,
433 .disable = &omap1_clk_disable_generic,
436 static struct clk dma_ck = {
437 /* No-idle controlled by "tc_ck" */
439 .parent = &tc_ck.clk,
440 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
441 CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
442 .recalc = &followparent_recalc,
443 .enable = &omap1_clk_enable_generic,
444 .disable = &omap1_clk_disable_generic,
447 static struct clk dma_lcdfree_ck = {
448 .name = "dma_lcdfree_ck",
449 .parent = &tc_ck.clk,
450 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
451 .recalc = &followparent_recalc,
452 .enable = &omap1_clk_enable_generic,
453 .disable = &omap1_clk_disable_generic,
456 static struct arm_idlect1_clk api_ck = {
459 .parent = &tc_ck.clk,
460 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
461 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
462 .enable_reg = (void __iomem *)ARM_IDLECT2,
463 .enable_bit = EN_APICK,
464 .recalc = &followparent_recalc,
465 .enable = &omap1_clk_enable_generic,
466 .disable = &omap1_clk_disable_generic,
471 static struct arm_idlect1_clk lb_ck = {
474 .parent = &tc_ck.clk,
475 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
477 .enable_reg = (void __iomem *)ARM_IDLECT2,
478 .enable_bit = EN_LBCK,
479 .recalc = &followparent_recalc,
480 .enable = &omap1_clk_enable_generic,
481 .disable = &omap1_clk_disable_generic,
486 static struct clk rhea1_ck = {
488 .parent = &tc_ck.clk,
489 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
490 .recalc = &followparent_recalc,
491 .enable = &omap1_clk_enable_generic,
492 .disable = &omap1_clk_disable_generic,
495 static struct clk rhea2_ck = {
497 .parent = &tc_ck.clk,
498 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
499 .recalc = &followparent_recalc,
500 .enable = &omap1_clk_enable_generic,
501 .disable = &omap1_clk_disable_generic,
504 static struct clk lcd_ck_16xx = {
507 .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL,
508 .enable_reg = (void __iomem *)ARM_IDLECT2,
509 .enable_bit = EN_LCDCK,
510 .rate_offset = CKCTL_LCDDIV_OFFSET,
511 .recalc = &omap1_ckctl_recalc,
512 .enable = &omap1_clk_enable_generic,
513 .disable = &omap1_clk_disable_generic,
516 static struct arm_idlect1_clk lcd_ck_1510 = {
520 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
521 RATE_CKCTL | CLOCK_IDLE_CONTROL,
522 .enable_reg = (void __iomem *)ARM_IDLECT2,
523 .enable_bit = EN_LCDCK,
524 .rate_offset = CKCTL_LCDDIV_OFFSET,
525 .recalc = &omap1_ckctl_recalc,
526 .enable = &omap1_clk_enable_generic,
527 .disable = &omap1_clk_disable_generic,
532 static struct clk uart1_1510 = {
534 /* Direct from ULPD, no real parent */
535 .parent = &armper_ck.clk,
537 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
538 ENABLE_REG_32BIT | ALWAYS_ENABLED |
539 CLOCK_NO_IDLE_PARENT,
540 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
541 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */
542 .set_rate = &omap1_set_uart_rate,
543 .recalc = &omap1_uart_recalc,
544 .enable = &omap1_clk_enable_generic,
545 .disable = &omap1_clk_disable_generic,
548 static struct uart_clk uart1_16xx = {
551 /* Direct from ULPD, no real parent */
552 .parent = &armper_ck.clk,
554 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED |
555 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
556 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
558 .enable = &omap1_clk_enable_uart_functional,
559 .disable = &omap1_clk_disable_uart_functional,
561 .sysc_addr = 0xfffb0054,
564 static struct clk uart2_ck = {
566 /* Direct from ULPD, no real parent */
567 .parent = &armper_ck.clk,
569 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
570 CLOCK_IN_OMAP310 | ENABLE_REG_32BIT |
571 ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,
572 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
573 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */
574 .set_rate = &omap1_set_uart_rate,
575 .recalc = &omap1_uart_recalc,
576 .enable = &omap1_clk_enable_generic,
577 .disable = &omap1_clk_disable_generic,
580 static struct clk uart3_1510 = {
582 /* Direct from ULPD, no real parent */
583 .parent = &armper_ck.clk,
585 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
586 ENABLE_REG_32BIT | ALWAYS_ENABLED |
587 CLOCK_NO_IDLE_PARENT,
588 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
589 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */
590 .set_rate = &omap1_set_uart_rate,
591 .recalc = &omap1_uart_recalc,
592 .enable = &omap1_clk_enable_generic,
593 .disable = &omap1_clk_disable_generic,
596 static struct uart_clk uart3_16xx = {
599 /* Direct from ULPD, no real parent */
600 .parent = &armper_ck.clk,
602 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED |
603 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
604 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
606 .enable = &omap1_clk_enable_uart_functional,
607 .disable = &omap1_clk_disable_uart_functional,
609 .sysc_addr = 0xfffb9854,
612 static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
614 /* Direct from ULPD, no parent */
616 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
617 CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT,
618 .enable_reg = (void __iomem *)ULPD_CLOCK_CTRL,
619 .enable_bit = USB_MCLK_EN_BIT,
620 .enable = &omap1_clk_enable_generic,
621 .disable = &omap1_clk_disable_generic,
624 static struct clk usb_hhc_ck1510 = {
625 .name = "usb_hhc_ck",
626 /* Direct from ULPD, no parent */
627 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
628 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
629 RATE_FIXED | ENABLE_REG_32BIT,
630 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
631 .enable_bit = USB_HOST_HHC_UHOST_EN,
632 .enable = &omap1_clk_enable_generic,
633 .disable = &omap1_clk_disable_generic,
636 static struct clk usb_hhc_ck16xx = {
637 .name = "usb_hhc_ck",
638 /* Direct from ULPD, no parent */
640 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
641 .flags = CLOCK_IN_OMAP16XX |
642 RATE_FIXED | ENABLE_REG_32BIT,
643 .enable_reg = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
644 .enable_bit = 8 /* UHOST_EN */,
645 .enable = &omap1_clk_enable_generic,
646 .disable = &omap1_clk_disable_generic,
649 static struct clk usb_dc_ck = {
651 /* Direct from ULPD, no parent */
653 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED,
654 .enable_reg = (void __iomem *)SOFT_REQ_REG,
656 .enable = &omap1_clk_enable_generic,
657 .disable = &omap1_clk_disable_generic,
660 static struct clk mclk_1510 = {
662 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
664 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
665 .enable_reg = (void __iomem *)SOFT_REQ_REG,
667 .enable = &omap1_clk_enable_generic,
668 .disable = &omap1_clk_disable_generic,
671 static struct clk mclk_16xx = {
673 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
674 .flags = CLOCK_IN_OMAP16XX,
675 .enable_reg = (void __iomem *)COM_CLK_DIV_CTRL_SEL,
676 .enable_bit = COM_ULPD_PLL_CLK_REQ,
677 .set_rate = &omap1_set_ext_clk_rate,
678 .round_rate = &omap1_round_ext_clk_rate,
679 .init = &omap1_init_ext_clk,
680 .enable = &omap1_clk_enable_generic,
681 .disable = &omap1_clk_disable_generic,
684 static struct clk bclk_1510 = {
686 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
688 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
689 .enable = &omap1_clk_enable_generic,
690 .disable = &omap1_clk_disable_generic,
693 static struct clk bclk_16xx = {
695 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
696 .flags = CLOCK_IN_OMAP16XX,
697 .enable_reg = (void __iomem *)SWD_CLK_DIV_CTRL_SEL,
698 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
699 .set_rate = &omap1_set_ext_clk_rate,
700 .round_rate = &omap1_round_ext_clk_rate,
701 .init = &omap1_init_ext_clk,
702 .enable = &omap1_clk_enable_generic,
703 .disable = &omap1_clk_disable_generic,
706 static struct clk mmc1_ck = {
709 /* Functional clock is direct from ULPD, interface clock is ARMPER */
710 .parent = &armper_ck.clk,
712 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
713 CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT |
714 CLOCK_NO_IDLE_PARENT,
715 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
717 .enable = &omap1_clk_enable_generic,
718 .disable = &omap1_clk_disable_generic,
721 static struct clk mmc2_ck = {
724 /* Functional clock is direct from ULPD, interface clock is ARMPER */
725 .parent = &armper_ck.clk,
727 .flags = CLOCK_IN_OMAP16XX |
728 RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
729 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
731 .enable = &omap1_clk_enable_generic,
732 .disable = &omap1_clk_disable_generic,
735 static struct clk virtual_ck_mpu = {
737 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
738 CLOCK_IN_OMAP310 | VIRTUAL_CLOCK | ALWAYS_ENABLED,
739 .parent = &arm_ck, /* Is smarter alias for */
740 .recalc = &followparent_recalc,
741 .set_rate = &omap1_select_table_rate,
742 .round_rate = &omap1_round_to_table_rate,
743 .enable = &omap1_clk_enable_generic,
744 .disable = &omap1_clk_disable_generic,
747 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
748 remains active during MPU idle whenever this is enabled */
749 static struct clk i2c_fck = {
752 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
753 VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT |
755 .parent = &armxor_ck.clk,
756 .recalc = &followparent_recalc,
757 .enable = &omap1_clk_enable_generic,
758 .disable = &omap1_clk_disable_generic,
761 static struct clk i2c_ick = {
764 .flags = CLOCK_IN_OMAP16XX |
765 VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT |
767 .parent = &armper_ck.clk,
768 .recalc = &followparent_recalc,
769 .enable = &omap1_clk_enable_generic,
770 .disable = &omap1_clk_disable_generic,
773 static struct clk * onchip_clks[] = {
774 /* non-ULPD clocks */
786 &arminth_ck1510, &arminth_ck16xx,
814 &usb_hhc_ck1510, &usb_hhc_ck16xx,
816 &mclk_1510, &mclk_16xx,
817 &bclk_1510, &bclk_16xx,