2 * linux/arch/arm/mach-omap1/clock.c
4 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
7 * Modified to use omap shared clock framework by
8 * Tony Lindgren <tony@atomide.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
22 #include <asm/mach-types.h>
23 #include <asm/clkdev.h>
27 #include <plat/clock.h>
28 #include <plat/sram.h>
29 #include <plat/clkdev_omap.h>
34 __u32 arm_idlect1_mask;
35 struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
37 /*-------------------------------------------------------------------------
38 * Omap1 specific clock functions
39 *-------------------------------------------------------------------------*/
41 unsigned long omap1_uart_recalc(struct clk *clk)
43 unsigned int val = __raw_readl(clk->enable_reg);
44 return val & clk->enable_bit ? 48000000 : 12000000;
47 unsigned long omap1_sossi_recalc(struct clk *clk)
49 u32 div = omap_readl(MOD_CONF_CTRL_1);
51 div = (div >> 17) & 0x7;
54 return clk->parent->rate / div;
57 static void omap1_clk_allow_idle(struct clk *clk)
59 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
61 if (!(clk->flags & CLOCK_IDLE_CONTROL))
64 if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
65 arm_idlect1_mask |= 1 << iclk->idlect_shift;
68 static void omap1_clk_deny_idle(struct clk *clk)
70 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
72 if (!(clk->flags & CLOCK_IDLE_CONTROL))
75 if (iclk->no_idle_count++ == 0)
76 arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
79 static __u16 verify_ckctl_value(__u16 newval)
81 /* This function checks for following limitations set
82 * by the hardware (all conditions must be true):
83 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
88 * In addition following rules are enforced:
92 * However, maximum frequencies are not checked for!
101 per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
102 lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
103 arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
104 dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
105 tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
106 dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
108 if (dspmmu_exp < dsp_exp)
109 dspmmu_exp = dsp_exp;
110 if (dspmmu_exp > dsp_exp+1)
111 dspmmu_exp = dsp_exp+1;
112 if (tc_exp < arm_exp)
114 if (tc_exp < dspmmu_exp)
116 if (tc_exp > lcd_exp)
118 if (tc_exp > per_exp)
122 newval |= per_exp << CKCTL_PERDIV_OFFSET;
123 newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
124 newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
125 newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
126 newval |= tc_exp << CKCTL_TCDIV_OFFSET;
127 newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
132 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
134 /* Note: If target frequency is too low, this function will return 4,
135 * which is invalid value. Caller must check for this value and act
138 * Note: This function does not check for following limitations set
139 * by the hardware (all conditions must be true):
140 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
145 unsigned long realrate;
149 parent = clk->parent;
150 if (unlikely(parent == NULL))
153 realrate = parent->rate;
154 for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
155 if (realrate <= rate)
164 unsigned long omap1_ckctl_recalc(struct clk *clk)
166 /* Calculate divisor encoded as 2-bit exponent */
167 int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
169 return clk->parent->rate / dsor;
172 unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
176 /* Calculate divisor encoded as 2-bit exponent
178 * The clock control bits are in DSP domain,
179 * so api_ck is needed for access.
180 * Note that DSP_CKCTL virt addr = phys addr, so
181 * we must use __raw_readw() instead of omap_readw().
183 omap1_clk_enable(api_ck_p);
184 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
185 omap1_clk_disable(api_ck_p);
187 return clk->parent->rate / dsor;
190 /* MPU virtual clock functions */
191 int omap1_select_table_rate(struct clk *clk, unsigned long rate)
193 /* Find the highest supported frequency <= rate and switch to it */
194 struct mpu_rate * ptr;
195 unsigned long dpll1_rate, ref_rate;
197 dpll1_rate = ck_dpll1_p->rate;
198 ref_rate = ck_ref_p->rate;
200 for (ptr = omap1_rate_table; ptr->rate; ptr++) {
201 if (ptr->xtal != ref_rate)
204 /* DPLL1 cannot be reprogrammed without risking system crash */
205 if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate)
208 /* Can check only after xtal frequency check */
209 if (ptr->rate <= rate)
217 * In most cases we should not need to reprogram DPLL.
218 * Reprogramming the DPLL is tricky, it must be done from SRAM.
219 * (on 730, bit 13 must always be 1)
221 if (cpu_is_omap7xx())
222 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
224 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
226 /* XXX Do we need to recalculate the tree below DPLL1 at this point? */
227 ck_dpll1_p->rate = ptr->pll_rate;
232 int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
237 dsor_exp = calc_dsor_exp(clk, rate);
243 regval = __raw_readw(DSP_CKCTL);
244 regval &= ~(3 << clk->rate_offset);
245 regval |= dsor_exp << clk->rate_offset;
246 __raw_writew(regval, DSP_CKCTL);
247 clk->rate = clk->parent->rate / (1 << dsor_exp);
252 long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
254 int dsor_exp = calc_dsor_exp(clk, rate);
259 return clk->parent->rate / (1 << dsor_exp);
262 int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
267 dsor_exp = calc_dsor_exp(clk, rate);
273 regval = omap_readw(ARM_CKCTL);
274 regval &= ~(3 << clk->rate_offset);
275 regval |= dsor_exp << clk->rate_offset;
276 regval = verify_ckctl_value(regval);
277 omap_writew(regval, ARM_CKCTL);
278 clk->rate = clk->parent->rate / (1 << dsor_exp);
282 long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
284 /* Find the highest supported frequency <= rate */
285 struct mpu_rate * ptr;
287 unsigned long ref_rate;
289 ref_rate = ck_ref_p->rate;
291 highest_rate = -EINVAL;
293 for (ptr = omap1_rate_table; ptr->rate; ptr++) {
294 if (ptr->xtal != ref_rate)
297 highest_rate = ptr->rate;
299 /* Can check only after xtal frequency check */
300 if (ptr->rate <= rate)
307 static unsigned calc_ext_dsor(unsigned long rate)
311 /* MCLK and BCLK divisor selection is not linear:
312 * freq = 96MHz / dsor
314 * RATIO_SEL range: dsor <-> RATIO_SEL
315 * 0..6: (RATIO_SEL+2) <-> (dsor-2)
316 * 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
317 * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
320 for (dsor = 2; dsor < 96; ++dsor) {
321 if ((dsor & 1) && dsor > 8)
323 if (rate >= 96000000 / dsor)
329 /* XXX Only needed on 1510 */
330 int omap1_set_uart_rate(struct clk *clk, unsigned long rate)
334 val = __raw_readl(clk->enable_reg);
335 if (rate == 12000000)
336 val &= ~(1 << clk->enable_bit);
337 else if (rate == 48000000)
338 val |= (1 << clk->enable_bit);
341 __raw_writel(val, clk->enable_reg);
347 /* External clock (MCLK & BCLK) functions */
348 int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate)
353 dsor = calc_ext_dsor(rate);
354 clk->rate = 96000000 / dsor;
356 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
358 ratio_bits = (dsor - 2) << 2;
360 ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd;
361 __raw_writew(ratio_bits, clk->enable_reg);
366 int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
370 unsigned long p_rate;
372 p_rate = clk->parent->rate;
373 /* Round towards slower frequency */
374 div = (p_rate + rate - 1) / rate;
376 if (div < 0 || div > 7)
379 l = omap_readl(MOD_CONF_CTRL_1);
382 omap_writel(l, MOD_CONF_CTRL_1);
384 clk->rate = p_rate / (div + 1);
389 long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate)
391 return 96000000 / calc_ext_dsor(rate);
394 void omap1_init_ext_clk(struct clk *clk)
399 /* Determine current rate and ensure clock is based on 96MHz APLL */
400 ratio_bits = __raw_readw(clk->enable_reg) & ~1;
401 __raw_writew(ratio_bits, clk->enable_reg);
403 ratio_bits = (ratio_bits & 0xfc) >> 2;
405 dsor = (ratio_bits - 6) * 2 + 8;
407 dsor = ratio_bits + 2;
409 clk-> rate = 96000000 / dsor;
412 int omap1_clk_enable(struct clk *clk)
416 if (clk->usecount++ == 0) {
418 ret = omap1_clk_enable(clk->parent);
422 if (clk->flags & CLOCK_NO_IDLE_PARENT)
423 omap1_clk_deny_idle(clk->parent);
426 ret = clk->ops->enable(clk);
429 omap1_clk_disable(clk->parent);
440 void omap1_clk_disable(struct clk *clk)
442 if (clk->usecount > 0 && !(--clk->usecount)) {
443 clk->ops->disable(clk);
444 if (likely(clk->parent)) {
445 omap1_clk_disable(clk->parent);
446 if (clk->flags & CLOCK_NO_IDLE_PARENT)
447 omap1_clk_allow_idle(clk->parent);
452 static int omap1_clk_enable_generic(struct clk *clk)
457 if (unlikely(clk->enable_reg == NULL)) {
458 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
463 if (clk->flags & ENABLE_REG_32BIT) {
464 regval32 = __raw_readl(clk->enable_reg);
465 regval32 |= (1 << clk->enable_bit);
466 __raw_writel(regval32, clk->enable_reg);
468 regval16 = __raw_readw(clk->enable_reg);
469 regval16 |= (1 << clk->enable_bit);
470 __raw_writew(regval16, clk->enable_reg);
476 static void omap1_clk_disable_generic(struct clk *clk)
481 if (clk->enable_reg == NULL)
484 if (clk->flags & ENABLE_REG_32BIT) {
485 regval32 = __raw_readl(clk->enable_reg);
486 regval32 &= ~(1 << clk->enable_bit);
487 __raw_writel(regval32, clk->enable_reg);
489 regval16 = __raw_readw(clk->enable_reg);
490 regval16 &= ~(1 << clk->enable_bit);
491 __raw_writew(regval16, clk->enable_reg);
495 const struct clkops clkops_generic = {
496 .enable = omap1_clk_enable_generic,
497 .disable = omap1_clk_disable_generic,
500 static int omap1_clk_enable_dsp_domain(struct clk *clk)
504 retval = omap1_clk_enable(api_ck_p);
506 retval = omap1_clk_enable_generic(clk);
507 omap1_clk_disable(api_ck_p);
513 static void omap1_clk_disable_dsp_domain(struct clk *clk)
515 if (omap1_clk_enable(api_ck_p) == 0) {
516 omap1_clk_disable_generic(clk);
517 omap1_clk_disable(api_ck_p);
521 const struct clkops clkops_dspck = {
522 .enable = omap1_clk_enable_dsp_domain,
523 .disable = omap1_clk_disable_dsp_domain,
526 static int omap1_clk_enable_uart_functional(struct clk *clk)
529 struct uart_clk *uclk;
531 ret = omap1_clk_enable_generic(clk);
533 /* Set smart idle acknowledgement mode */
534 uclk = (struct uart_clk *)clk;
535 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
542 static void omap1_clk_disable_uart_functional(struct clk *clk)
544 struct uart_clk *uclk;
546 /* Set force idle acknowledgement mode */
547 uclk = (struct uart_clk *)clk;
548 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
550 omap1_clk_disable_generic(clk);
553 const struct clkops clkops_uart = {
554 .enable = omap1_clk_enable_uart_functional,
555 .disable = omap1_clk_disable_uart_functional,
558 long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
560 if (clk->round_rate != NULL)
561 return clk->round_rate(clk, rate);
566 int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
571 ret = clk->set_rate(clk, rate);
575 /*-------------------------------------------------------------------------
576 * Omap1 clock reset and init functions
577 *-------------------------------------------------------------------------*/
579 #ifdef CONFIG_OMAP_RESET_CLOCKS
581 void omap1_clk_disable_unused(struct clk *clk)
585 /* Clocks in the DSP domain need api_ck. Just assume bootloader
586 * has not enabled any DSP clocks */
587 if (clk->enable_reg == DSP_IDLECT2) {
588 printk(KERN_INFO "Skipping reset check for DSP domain "
589 "clock \"%s\"\n", clk->name);
593 /* Is the clock already disabled? */
594 if (clk->flags & ENABLE_REG_32BIT)
595 regval32 = __raw_readl(clk->enable_reg);
597 regval32 = __raw_readw(clk->enable_reg);
599 if ((regval32 & (1 << clk->enable_bit)) == 0)
602 printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
603 clk->ops->disable(clk);