2 * based on code from the following
3 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
5 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
15 #include <linux/init.h>
16 #include <linux/platform_device.h>
17 #include <linux/i2c.h>
18 #include <linux/gpio.h>
19 #include <linux/leds.h>
20 #include <linux/input.h>
21 #include <linux/delay.h>
23 #include <linux/fsl_devices.h>
24 #include <linux/spi/flash.h>
25 #include <linux/spi/spi.h>
26 #include <linux/mfd/mc13892.h>
27 #include <linux/regulator/machine.h>
28 #include <linux/regulator/consumer.h>
30 #include <mach/common.h>
31 #include <mach/hardware.h>
32 #include <mach/iomux-mx51.h>
34 #include <mach/mxc_ehci.h>
36 #include <linux/usb/otg.h>
37 #include <linux/usb/ulpi.h>
38 #include <mach/ulpi.h>
41 #include <asm/setup.h>
42 #include <asm/mach-types.h>
43 #include <asm/mach/arch.h>
44 #include <asm/mach/time.h>
46 #include "devices-imx51.h"
49 #include "cpu_op-mx51.h"
51 #define MX51_USB_CTRL_1_OFFSET 0x10
52 #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
53 #define MX51_USB_PLL_DIV_19_2_MHZ 0x01
55 #define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5)
56 #define EFIKAMX_USBH1_STP IMX_GPIO_NR(1, 27)
58 #define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24)
59 #define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25)
61 #define EFIKAMX_PMIC IMX_GPIO_NR(1, 6)
63 static iomux_v3_cfg_t mx51efika_pads[] = {
65 MX51_PAD_UART1_RXD__UART1_RXD,
66 MX51_PAD_UART1_TXD__UART1_TXD,
67 MX51_PAD_UART1_RTS__UART1_RTS,
68 MX51_PAD_UART1_CTS__UART1_CTS,
71 MX51_PAD_SD1_CMD__SD1_CMD,
72 MX51_PAD_SD1_CLK__SD1_CLK,
73 MX51_PAD_SD1_DATA0__SD1_DATA0,
74 MX51_PAD_SD1_DATA1__SD1_DATA1,
75 MX51_PAD_SD1_DATA2__SD1_DATA2,
76 MX51_PAD_SD1_DATA3__SD1_DATA3,
79 MX51_PAD_SD2_CMD__SD2_CMD,
80 MX51_PAD_SD2_CLK__SD2_CLK,
81 MX51_PAD_SD2_DATA0__SD2_DATA0,
82 MX51_PAD_SD2_DATA1__SD2_DATA1,
83 MX51_PAD_SD2_DATA2__SD2_DATA2,
84 MX51_PAD_SD2_DATA3__SD2_DATA3,
87 MX51_PAD_GPIO1_0__SD1_CD,
88 MX51_PAD_GPIO1_1__SD1_WP,
89 MX51_PAD_GPIO1_7__SD2_WP,
90 MX51_PAD_GPIO1_8__SD2_CD,
93 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
94 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
95 MX51_PAD_CSPI1_SS0__GPIO4_24,
96 MX51_PAD_CSPI1_SS1__GPIO4_25,
97 MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
98 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
99 MX51_PAD_GPIO1_6__GPIO1_6,
102 MX51_PAD_USBH1_CLK__USBH1_CLK,
103 MX51_PAD_USBH1_DIR__USBH1_DIR,
104 MX51_PAD_USBH1_NXT__USBH1_NXT,
105 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
106 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
107 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
108 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
109 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
110 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
111 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
112 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
115 MX51_PAD_GPIO1_5__GPIO1_5,
118 MX51_PAD_EIM_A22__GPIO2_16,
119 MX51_PAD_EIM_A16__GPIO2_10,
122 MX51_PAD_EIM_D27__GPIO2_9,
126 static const struct imxuart_platform_data uart_pdata = {
127 .flags = IMXUART_HAVE_RTSCTS,
130 /* This function is board specific as the bit mask for the plldiv will also
131 * be different for other Freescale SoCs, thus a common bitmask is not
132 * possible and cannot get place in /plat-mxc/ehci.c.
134 static int initialize_otg_port(struct platform_device *pdev)
137 void __iomem *usb_base;
138 void __iomem *usbother_base;
139 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
142 usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
144 /* Set the PHY clock to 19.2MHz */
145 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
146 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
147 v |= MX51_USB_PLL_DIV_19_2_MHZ;
148 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
153 return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
156 static struct mxc_usbh_platform_data dr_utmi_config = {
157 .init = initialize_otg_port,
158 .portsc = MXC_EHCI_UTMI_16BIT,
161 static int initialize_usbh1_port(struct platform_device *pdev)
163 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
164 iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
166 void __iomem *usb_base;
167 void __iomem *socregs_base;
169 mxc_iomux_v3_setup_pad(usbh1gpio);
170 gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
171 gpio_direction_output(EFIKAMX_USBH1_STP, 0);
173 gpio_set_value(EFIKAMX_USBH1_STP, 1);
176 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
177 socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
179 /* The clock for the USBH1 ULPI port will come externally */
181 v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
182 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
183 socregs_base + MX51_USB_CTRL_1_OFFSET);
187 gpio_free(EFIKAMX_USBH1_STP);
188 mxc_iomux_v3_setup_pad(usbh1stp);
192 return mx51_initialize_usb_hw(0, MXC_EHCI_ITC_NO_THRESHOLD);
195 static struct mxc_usbh_platform_data usbh1_config = {
196 .init = initialize_usbh1_port,
197 .portsc = MXC_EHCI_MODE_ULPI,
200 static void mx51_efika_hubreset(void)
202 gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst");
203 gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1);
205 gpio_set_value(EFIKAMX_USB_HUB_RESET, 0);
207 gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
210 static void __init mx51_efika_usb(void)
212 mx51_efika_hubreset();
214 /* pulling it low, means no USB at all... */
215 gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset");
216 gpio_direction_output(EFIKA_USB_PHY_RESET, 0);
218 gpio_set_value(EFIKA_USB_PHY_RESET, 1);
220 usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
221 ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
223 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
224 if (usbh1_config.otg)
225 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
228 static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
236 .offset = MTDPART_OFS_APPEND,
241 static struct flash_platform_data mx51_efika_spi_flash_data = {
243 .parts = mx51_efika_spi_nor_partitions,
244 .nr_parts = ARRAY_SIZE(mx51_efika_spi_nor_partitions),
245 .type = "sst25vf032b",
248 static struct regulator_consumer_supply sw1_consumers[] = {
254 static struct regulator_consumer_supply vdig_consumers[] = {
256 REGULATOR_SUPPLY("VDDA", "1-000a"),
257 REGULATOR_SUPPLY("VDDD", "1-000a"),
260 static struct regulator_consumer_supply vvideo_consumers[] = {
262 REGULATOR_SUPPLY("VDDIO", "1-000a"),
265 static struct regulator_consumer_supply vsd_consumers[] = {
266 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.0"),
267 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"),
270 static struct regulator_consumer_supply pwgt1_consumer[] = {
276 static struct regulator_consumer_supply pwgt2_consumer[] = {
282 static struct regulator_consumer_supply coincell_consumer[] = {
284 .supply = "coincell",
288 static struct regulator_init_data sw1_init = {
293 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
294 .valid_modes_mask = 0,
299 .mode = REGULATOR_MODE_NORMAL,
303 .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
304 .consumer_supplies = sw1_consumers,
307 static struct regulator_init_data sw2_init = {
312 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
317 .mode = REGULATOR_MODE_NORMAL,
323 static struct regulator_init_data sw3_init = {
328 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
334 static struct regulator_init_data sw4_init = {
339 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
345 static struct regulator_init_data viohi_init = {
353 static struct regulator_init_data vusb_init = {
361 static struct regulator_init_data swbst_init = {
367 static struct regulator_init_data vdig_init = {
373 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
377 .num_consumer_supplies = ARRAY_SIZE(vdig_consumers),
378 .consumer_supplies = vdig_consumers,
381 static struct regulator_init_data vpll_init = {
387 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
393 static struct regulator_init_data vusb2_init = {
398 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
404 static struct regulator_init_data vvideo_init = {
410 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
414 .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers),
415 .consumer_supplies = vvideo_consumers,
418 static struct regulator_init_data vaudio_init = {
424 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
429 static struct regulator_init_data vsd_init = {
435 REGULATOR_CHANGE_VOLTAGE,
438 .num_consumer_supplies = ARRAY_SIZE(vsd_consumers),
439 .consumer_supplies = vsd_consumers,
442 static struct regulator_init_data vcam_init = {
448 REGULATOR_CHANGE_VOLTAGE |
449 REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
450 .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
455 static struct regulator_init_data vgen1_init = {
461 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
467 static struct regulator_init_data vgen2_init = {
473 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
479 static struct regulator_init_data vgen3_init = {
485 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
491 static struct regulator_init_data gpo1_init = {
497 static struct regulator_init_data gpo2_init = {
503 static struct regulator_init_data gpo3_init = {
509 static struct regulator_init_data gpo4_init = {
515 static struct regulator_init_data pwgt1_init = {
517 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
520 .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer),
521 .consumer_supplies = pwgt1_consumer,
524 static struct regulator_init_data pwgt2_init = {
526 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
529 .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer),
530 .consumer_supplies = pwgt2_consumer,
533 static struct regulator_init_data vcoincell_init = {
539 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
541 .num_consumer_supplies = ARRAY_SIZE(coincell_consumer),
542 .consumer_supplies = coincell_consumer,
545 static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
546 { .id = MC13892_SW1, .init_data = &sw1_init },
547 { .id = MC13892_SW2, .init_data = &sw2_init },
548 { .id = MC13892_SW3, .init_data = &sw3_init },
549 { .id = MC13892_SW4, .init_data = &sw4_init },
550 { .id = MC13892_SWBST, .init_data = &swbst_init },
551 { .id = MC13892_VIOHI, .init_data = &viohi_init },
552 { .id = MC13892_VPLL, .init_data = &vpll_init },
553 { .id = MC13892_VDIG, .init_data = &vdig_init },
554 { .id = MC13892_VSD, .init_data = &vsd_init },
555 { .id = MC13892_VUSB2, .init_data = &vusb2_init },
556 { .id = MC13892_VVIDEO, .init_data = &vvideo_init },
557 { .id = MC13892_VAUDIO, .init_data = &vaudio_init },
558 { .id = MC13892_VCAM, .init_data = &vcam_init },
559 { .id = MC13892_VGEN1, .init_data = &vgen1_init },
560 { .id = MC13892_VGEN2, .init_data = &vgen2_init },
561 { .id = MC13892_VGEN3, .init_data = &vgen3_init },
562 { .id = MC13892_VUSB, .init_data = &vusb_init },
563 { .id = MC13892_GPO1, .init_data = &gpo1_init },
564 { .id = MC13892_GPO2, .init_data = &gpo2_init },
565 { .id = MC13892_GPO3, .init_data = &gpo3_init },
566 { .id = MC13892_GPO4, .init_data = &gpo4_init },
567 { .id = MC13892_PWGT1SPI, .init_data = &pwgt1_init },
568 { .id = MC13892_PWGT2SPI, .init_data = &pwgt2_init },
569 { .id = MC13892_VCOINCELL, .init_data = &vcoincell_init },
572 static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
573 .flags = MC13XXX_USE_RTC | MC13XXX_USE_REGULATOR,
575 .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
576 .regulators = mx51_efika_regulators,
580 static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
582 .modalias = "m25p80",
583 .max_speed_hz = 25000000,
586 .platform_data = &mx51_efika_spi_flash_data,
590 .modalias = "mc13892",
591 .max_speed_hz = 1000000,
594 .platform_data = &mx51_efika_mc13892_data,
595 .irq = gpio_to_irq(EFIKAMX_PMIC),
599 static int mx51_efika_spi_cs[] = {
604 static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
605 .chipselect = mx51_efika_spi_cs,
606 .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
609 void __init efika_board_common_init(void)
611 mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
612 ARRAY_SIZE(mx51efika_pads));
613 imx51_add_imx_uart(0, &uart_pdata);
615 imx51_add_sdhci_esdhc_imx(0, NULL);
617 /* FIXME: comes from original code. check this. */
618 if (mx51_revision() < IMX_CHIP_REVISION_2_0)
619 sw2_init.constraints.state_mem.uV = 1100000;
620 else if (mx51_revision() == IMX_CHIP_REVISION_2_0) {
621 sw2_init.constraints.state_mem.uV = 1250000;
622 sw1_init.constraints.state_mem.uV = 1000000;
624 if (machine_is_mx51_efikasb())
625 vgen1_init.constraints.max_uV = 1200000;
627 gpio_request(EFIKAMX_PMIC, "pmic irq");
628 gpio_direction_input(EFIKAMX_PMIC);
629 spi_register_board_info(mx51_efika_spi_board_info,
630 ARRAY_SIZE(mx51_efika_spi_board_info));
631 imx51_add_ecspi(0, &mx51_efika_spi_pdata);
633 #if defined(CONFIG_CPU_FREQ_IMX)
634 get_cpu_op = mx51_get_cpu_op;