2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
11 * Create static mapping between physical to virtual memory.
15 #include <linux/init.h>
17 #include <asm/mach/map.h>
19 #include <mach/hardware.h>
20 #include <mach/common.h>
21 #include <mach/devices-common.h>
22 #include <mach/iomux-v3.h>
25 * Define the MX50 memory map.
27 static struct map_desc mx50_io_desc[] __initdata = {
28 imx_map_entry(MX50, TZIC, MT_DEVICE),
29 imx_map_entry(MX50, SPBA0, MT_DEVICE),
30 imx_map_entry(MX50, AIPS1, MT_DEVICE),
31 imx_map_entry(MX50, AIPS2, MT_DEVICE),
35 * Define the MX51 memory map.
37 static struct map_desc mx51_io_desc[] __initdata = {
38 imx_map_entry(MX51, TZIC, MT_DEVICE),
39 imx_map_entry(MX51, IRAM, MT_DEVICE),
40 imx_map_entry(MX51, AIPS1, MT_DEVICE),
41 imx_map_entry(MX51, SPBA0, MT_DEVICE),
42 imx_map_entry(MX51, AIPS2, MT_DEVICE),
46 * Define the MX53 memory map.
48 static struct map_desc mx53_io_desc[] __initdata = {
49 imx_map_entry(MX53, TZIC, MT_DEVICE),
50 imx_map_entry(MX53, AIPS1, MT_DEVICE),
51 imx_map_entry(MX53, SPBA0, MT_DEVICE),
52 imx_map_entry(MX53, AIPS2, MT_DEVICE),
56 * This function initializes the memory map. It is called during the
57 * system startup to create static physical to virtual memory mappings
60 void __init mx50_map_io(void)
62 iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
65 void __init mx51_map_io(void)
67 iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
70 void __init mx53_map_io(void)
72 iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
75 void __init imx50_init_early(void)
77 mxc_set_cpu_type(MXC_CPU_MX50);
78 mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
79 mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
82 void __init imx51_init_early(void)
84 mxc_set_cpu_type(MXC_CPU_MX51);
85 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
86 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
89 void __init imx53_init_early(void)
91 mxc_set_cpu_type(MXC_CPU_MX53);
92 mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
93 mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
96 void __init mx50_init_irq(void)
98 tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
101 void __init mx51_init_irq(void)
103 tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
106 void __init mx53_init_irq(void)
108 tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
111 static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
113 .uart_2_mcu_addr = 817,
114 .mcu_2_app_addr = 747,
115 .mcu_2_shp_addr = 961,
116 .ata_2_mcu_addr = 1473,
117 .mcu_2_ata_addr = 1392,
118 .app_2_per_addr = 1033,
119 .app_2_mcu_addr = 683,
120 .shp_2_per_addr = 1251,
121 .shp_2_mcu_addr = 892,
124 static struct sdma_platform_data imx51_sdma_pdata __initdata = {
125 .fw_name = "sdma-imx51.bin",
126 .script_addrs = &imx51_sdma_script,
129 static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
131 .app_2_mcu_addr = 683,
132 .mcu_2_app_addr = 747,
133 .uart_2_mcu_addr = 817,
134 .shp_2_mcu_addr = 891,
135 .mcu_2_shp_addr = 960,
136 .uartsh_2_mcu_addr = 1032,
137 .spdif_2_mcu_addr = 1100,
138 .mcu_2_spdif_addr = 1134,
139 .firi_2_mcu_addr = 1193,
140 .mcu_2_firi_addr = 1290,
143 static struct sdma_platform_data imx53_sdma_pdata __initdata = {
144 .fw_name = "sdma-imx53.bin",
145 .script_addrs = &imx53_sdma_script,
148 void __init imx50_soc_init(void)
150 /* i.mx50 has the i.mx31 type gpio */
151 mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
152 mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
153 mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
154 mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
155 mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
156 mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
159 void __init imx51_soc_init(void)
161 /* i.mx51 has the i.mx31 type gpio */
162 mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO1_LOW, MX51_MXC_INT_GPIO1_HIGH);
163 mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO2_LOW, MX51_MXC_INT_GPIO2_HIGH);
164 mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO3_LOW, MX51_MXC_INT_GPIO3_HIGH);
165 mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO4_LOW, MX51_MXC_INT_GPIO4_HIGH);
167 /* i.mx51 has the i.mx35 type sdma */
168 imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
171 void __init imx53_soc_init(void)
173 /* i.mx53 has the i.mx31 type gpio */
174 mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
175 mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
176 mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
177 mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
178 mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
179 mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
180 mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
182 /* i.mx53 has the i.mx35 type sdma */
183 imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);