2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
11 * This file contains the CPU initialization code.
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <mach/hardware.h>
21 static int cpu_silicon_rev = -1;
25 static int get_mx51_srev(void)
27 void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
28 u32 rev = readl(iim_base + IIM_SREV) & 0xff;
31 return IMX_CHIP_REVISION_2_0;
33 return IMX_CHIP_REVISION_3_0;
39 * the silicon revision of the cpu
40 * -EINVAL - not a mx51
42 int mx51_revision(void)
47 if (cpu_silicon_rev == -1)
48 cpu_silicon_rev = get_mx51_srev();
50 return cpu_silicon_rev;
52 EXPORT_SYMBOL(mx51_revision);
57 * All versions of the silicon before Rev. 3 have broken NEON implementations.
58 * Dependent on link order - so the assumption is that vfp_init is called
61 static int __init mx51_neon_fixup(void)
66 if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) {
67 elf_hwcap &= ~HWCAP_NEON;
68 pr_info("Turning off NEON support, detected broken NEON implementation\n");
73 late_initcall(mx51_neon_fixup);
76 static int get_mx53_srev(void)
78 void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
79 u32 rev = readl(iim_base + IIM_SREV) & 0xff;
83 return IMX_CHIP_REVISION_1_0;
85 return IMX_CHIP_REVISION_2_0;
87 return IMX_CHIP_REVISION_2_1;
89 return IMX_CHIP_REVISION_UNKNOWN;
95 * the silicon revision of the cpu
96 * -EINVAL - not a mx53
98 int mx53_revision(void)
103 if (cpu_silicon_rev == -1)
104 cpu_silicon_rev = get_mx53_srev();
106 return cpu_silicon_rev;
108 EXPORT_SYMBOL(mx53_revision);
110 static int __init post_cpu_init(void)
115 if (cpu_is_mx51() || cpu_is_mx53()) {
117 base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
119 base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
121 __raw_writel(0x0, base + 0x40);
122 __raw_writel(0x0, base + 0x44);
123 __raw_writel(0x0, base + 0x48);
124 __raw_writel(0x0, base + 0x4C);
125 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
126 __raw_writel(reg, base + 0x50);
129 base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
131 base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
133 __raw_writel(0x0, base + 0x40);
134 __raw_writel(0x0, base + 0x44);
135 __raw_writel(0x0, base + 0x48);
136 __raw_writel(0x0, base + 0x4C);
137 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
138 __raw_writel(reg, base + 0x50);
144 postcore_initcall(post_cpu_init);