2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
11 * This file contains the CPU initialization code.
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <mach/hardware.h>
21 static int mx5_cpu_rev = -1;
24 #define MX50_HW_ADADIG_DIGPROG 0xB0
26 static int get_mx51_srev(void)
28 void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
29 u32 rev = readl(iim_base + IIM_SREV) & 0xff;
33 return IMX_CHIP_REVISION_2_0;
35 return IMX_CHIP_REVISION_3_0;
37 return IMX_CHIP_REVISION_UNKNOWN;
43 * the silicon revision of the cpu
44 * -EINVAL - not a mx51
46 int mx51_revision(void)
51 if (mx5_cpu_rev == -1)
52 mx5_cpu_rev = get_mx51_srev();
56 EXPORT_SYMBOL(mx51_revision);
61 * All versions of the silicon before Rev. 3 have broken NEON implementations.
62 * Dependent on link order - so the assumption is that vfp_init is called
65 static int __init mx51_neon_fixup(void)
70 if (mx51_revision() < IMX_CHIP_REVISION_3_0 &&
71 (elf_hwcap & HWCAP_NEON)) {
72 elf_hwcap &= ~HWCAP_NEON;
73 pr_info("Turning off NEON support, detected broken NEON implementation\n");
78 late_initcall(mx51_neon_fixup);
81 static int get_mx53_srev(void)
83 void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
84 u32 rev = readl(iim_base + IIM_SREV) & 0xff;
88 return IMX_CHIP_REVISION_1_0;
90 return IMX_CHIP_REVISION_2_0;
92 return IMX_CHIP_REVISION_2_1;
94 return IMX_CHIP_REVISION_UNKNOWN;
100 * the silicon revision of the cpu
101 * -EINVAL - not a mx53
103 int mx53_revision(void)
108 if (mx5_cpu_rev == -1)
109 mx5_cpu_rev = get_mx53_srev();
113 EXPORT_SYMBOL(mx53_revision);
115 static int get_mx50_srev(void)
117 void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K);
121 mx5_cpu_rev = -EINVAL;
125 rev = readl(anatop + MX50_HW_ADADIG_DIGPROG);
130 return IMX_CHIP_REVISION_1_0;
132 return IMX_CHIP_REVISION_1_1;
138 * the silicon revision of the cpu
139 * -EINVAL - not a mx50
141 int mx50_revision(void)
146 if (mx5_cpu_rev == -1)
147 mx5_cpu_rev = get_mx50_srev();
151 EXPORT_SYMBOL(mx50_revision);
153 static int __init post_cpu_init(void)
158 if (cpu_is_mx51() || cpu_is_mx53()) {
160 base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
162 base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
164 __raw_writel(0x0, base + 0x40);
165 __raw_writel(0x0, base + 0x44);
166 __raw_writel(0x0, base + 0x48);
167 __raw_writel(0x0, base + 0x4C);
168 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
169 __raw_writel(reg, base + 0x50);
172 base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
174 base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
176 __raw_writel(0x0, base + 0x40);
177 __raw_writel(0x0, base + 0x44);
178 __raw_writel(0x0, base + 0x48);
179 __raw_writel(0x0, base + 0x4C);
180 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
181 __raw_writel(reg, base + 0x50);
187 postcore_initcall(post_cpu_init);