3 * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
5 * based on board-mx51_babbage.c which is
6 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/i2c.h>
20 #include <linux/i2c/tsc2007.h>
21 #include <linux/gpio.h>
22 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/i2c-gpio.h>
27 #include <linux/spi/spi.h>
28 #include <linux/can/platform/mcp251x.h>
30 #include <mach/eukrea-baseboards.h>
31 #include <mach/common.h>
32 #include <mach/hardware.h>
33 #include <mach/iomux-mx51.h>
36 #include <asm/setup.h>
37 #include <asm/mach-types.h>
38 #include <asm/mach/arch.h>
39 #include <asm/mach/time.h>
41 #include "devices-imx51.h"
42 #include "cpu_op-mx51.h"
44 #define USBH1_RST IMX_GPIO_NR(2, 28)
45 #define ETH_RST IMX_GPIO_NR(2, 31)
46 #define TSC2007_IRQGPIO IMX_GPIO_NR(3, 12)
47 #define CAN_IRQGPIO IMX_GPIO_NR(1, 1)
48 #define CAN_RST IMX_GPIO_NR(4, 15)
49 #define CAN_NCS IMX_GPIO_NR(4, 24)
50 #define CAN_RXOBF IMX_GPIO_NR(1, 4)
51 #define CAN_RX1BF IMX_GPIO_NR(1, 6)
52 #define CAN_TXORTS IMX_GPIO_NR(1, 7)
53 #define CAN_TX1RTS IMX_GPIO_NR(1, 8)
54 #define CAN_TX2RTS IMX_GPIO_NR(1, 9)
55 #define I2C_SCL IMX_GPIO_NR(4, 16)
56 #define I2C_SDA IMX_GPIO_NR(4, 17)
59 #define MX51_USB_CTRL_1_OFFSET 0x10
60 #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
62 #define MX51_USB_PLLDIV_12_MHZ 0x00
63 #define MX51_USB_PLL_DIV_19_2_MHZ 0x01
64 #define MX51_USB_PLL_DIV_24_MHZ 0x02
66 static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
68 MX51_PAD_UART1_RXD__UART1_RXD,
69 MX51_PAD_UART1_TXD__UART1_TXD,
70 MX51_PAD_UART1_RTS__UART1_RTS,
71 MX51_PAD_UART1_CTS__UART1_CTS,
74 MX51_PAD_USBH1_CLK__USBH1_CLK,
75 MX51_PAD_USBH1_DIR__USBH1_DIR,
76 MX51_PAD_USBH1_NXT__USBH1_NXT,
77 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
78 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
79 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
80 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
81 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
82 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
83 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
84 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
85 MX51_PAD_USBH1_STP__USBH1_STP,
86 MX51_PAD_EIM_CS3__GPIO2_28, /* PHY nRESET */
89 MX51_PAD_EIM_DTACK__GPIO2_31, /* PHY nRESET */
92 MX51_PAD_I2C1_CLK__GPIO4_16,
93 MX51_PAD_I2C1_DAT__GPIO4_17,
96 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
97 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
98 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
99 MX51_PAD_CSPI1_SS0__GPIO4_24, /* nCS */
100 MX51_PAD_CSI2_PIXCLK__GPIO4_15, /* nReset */
101 MX51_PAD_GPIO1_1__GPIO1_1, /* IRQ */
102 MX51_PAD_GPIO1_4__GPIO1_4, /* Control signals */
103 MX51_PAD_GPIO1_6__GPIO1_6,
104 MX51_PAD_GPIO1_7__GPIO1_7,
105 MX51_PAD_GPIO1_8__GPIO1_8,
106 MX51_PAD_GPIO1_9__GPIO1_9,
110 _MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
111 PAD_CTL_PKE | PAD_CTL_SRE_FAST |
112 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
115 static const struct imxuart_platform_data uart_pdata __initconst = {
116 .flags = IMXUART_HAVE_RTSCTS,
119 static struct tsc2007_platform_data tsc2007_info = {
124 static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
126 I2C_BOARD_INFO("pcf8563", 0x51),
128 I2C_BOARD_INFO("tsc2007", 0x49),
130 .platform_data = &tsc2007_info,
131 .irq = gpio_to_irq(TSC2007_IRQGPIO),
135 static const struct mxc_nand_platform_data
136 eukrea_cpuimx51sd_nand_board_info __initconst = {
142 /* This function is board specific as the bit mask for the plldiv will also
143 be different for other Freescale SoCs, thus a common bitmask is not
144 possible and cannot get place in /plat-mxc/ehci.c.*/
145 static int initialize_otg_port(struct platform_device *pdev)
148 void __iomem *usb_base;
149 void __iomem *usbother_base;
151 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
154 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
156 /* Set the PHY clock to 19.2MHz */
157 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
158 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
159 v |= MX51_USB_PLL_DIV_19_2_MHZ;
160 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
165 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
168 static int initialize_usbh1_port(struct platform_device *pdev)
171 void __iomem *usb_base;
172 void __iomem *usbother_base;
174 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
177 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
179 /* The clock for the USBH1 ULPI port will come from the PHY. */
180 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
181 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
182 usbother_base + MX51_USB_CTRL_1_OFFSET);
187 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
188 MXC_EHCI_ITC_NO_THRESHOLD);
191 static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
192 .init = initialize_otg_port,
193 .portsc = MXC_EHCI_UTMI_16BIT,
196 static const struct fsl_usb2_platform_data usb_pdata __initconst = {
197 .operating_mode = FSL_USB2_DR_DEVICE,
198 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
201 static const struct mxc_usbh_platform_data usbh1_config __initconst = {
202 .init = initialize_usbh1_port,
203 .portsc = MXC_EHCI_MODE_ULPI,
206 static int otg_mode_host;
208 static int __init eukrea_cpuimx51sd_otg_mode(char *options)
210 if (!strcmp(options, "host"))
212 else if (!strcmp(options, "device"))
215 pr_info("otg_mode neither \"host\" nor \"device\". "
216 "Defaulting to device\n");
219 __setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
221 static struct i2c_gpio_platform_data pdata = {
223 .sda_is_open_drain = 0,
225 .scl_is_open_drain = 0,
229 static struct platform_device hsi2c_gpio_device = {
232 .dev.platform_data = &pdata,
235 static struct mcp251x_platform_data mcp251x_info = {
236 .oscillator_frequency = 24E6,
239 static struct spi_board_info cpuimx51sd_spi_device[] = {
241 .modalias = "mcp2515",
242 .max_speed_hz = 10000000,
246 .platform_data = &mcp251x_info,
247 .irq = gpio_to_irq(CAN_IRQGPIO)
251 static int cpuimx51sd_spi1_cs[] = {
255 static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
256 .chipselect = cpuimx51sd_spi1_cs,
257 .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
260 static struct platform_device *platform_devices[] __initdata = {
264 static void __init eukrea_cpuimx51sd_init(void)
268 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
269 ARRAY_SIZE(eukrea_cpuimx51sd_pads));
271 #if defined(CONFIG_CPU_FREQ_IMX)
272 get_cpu_op = mx51_get_cpu_op;
275 imx51_add_imx_uart(0, &uart_pdata);
276 imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
278 gpio_request(ETH_RST, "eth_rst");
279 gpio_set_value(ETH_RST, 1);
282 gpio_request(CAN_IRQGPIO, "can_irq");
283 gpio_direction_input(CAN_IRQGPIO);
284 gpio_free(CAN_IRQGPIO);
285 gpio_request(CAN_NCS, "can_ncs");
286 gpio_direction_output(CAN_NCS, 1);
288 gpio_request(CAN_RST, "can_rst");
289 gpio_direction_output(CAN_RST, 0);
291 gpio_set_value(CAN_RST, 1);
292 imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
293 spi_register_board_info(cpuimx51sd_spi_device,
294 ARRAY_SIZE(cpuimx51sd_spi_device));
296 gpio_request(TSC2007_IRQGPIO, "tsc2007_irq");
297 gpio_direction_input(TSC2007_IRQGPIO);
298 gpio_free(TSC2007_IRQGPIO);
300 i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
301 ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
302 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
305 imx51_add_mxc_ehci_otg(&dr_utmi_config);
307 initialize_otg_port(NULL);
308 imx51_add_fsl_usb2_udc(&usb_pdata);
311 gpio_request(USBH1_RST, "usb_rst");
312 gpio_direction_output(USBH1_RST, 0);
314 gpio_set_value(USBH1_RST, 1);
315 imx51_add_mxc_ehci_hs(1, &usbh1_config);
317 #ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
318 eukrea_mbimxsd51_baseboard_init();
322 static void __init eukrea_cpuimx51sd_timer_init(void)
324 mx51_clocks_init(32768, 24000000, 22579200, 0);
327 static struct sys_timer mxc_timer = {
328 .init = eukrea_cpuimx51sd_timer_init,
331 MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
332 /* Maintainer: Eric Bénard <eric@eukrea.com> */
333 .boot_params = MX51_PHYS_OFFSET + 0x100,
334 .map_io = mx51_map_io,
335 .init_early = imx51_init_early,
336 .init_irq = mx51_init_irq,
338 .init_machine = eukrea_cpuimx51sd_init,