2 * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/types.h>
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/memory.h>
19 #include <linux/platform_device.h>
20 #include <linux/mtd/physmap.h>
21 #include <linux/mtd/nand.h>
22 #include <linux/gpio.h>
24 #include <mach/hardware.h>
25 #include <mach/irqs.h>
26 #include <asm/mach-types.h>
27 #include <asm/mach/arch.h>
28 #include <asm/mach/time.h>
29 #include <asm/mach/map.h>
30 #include <mach/common.h>
32 #include <asm/setup.h>
33 #include <mach/iomux-mx3.h>
35 #include "devices-imx31.h"
39 #define QONG_FPGA_VERSION(major, minor, rev) \
40 (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
42 #define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR
43 #define QONG_FPGA_PERIPH_SIZE (1 << 24)
45 #define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR
46 #define QONG_FPGA_CTRL_SIZE 0x10
47 /* FPGA control registers */
48 #define QONG_FPGA_CTRL_VERSION 0x00
50 #define QONG_DNET_ID 1
51 #define QONG_DNET_BASEADDR \
52 (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
53 #define QONG_DNET_SIZE 0x00001000
55 #define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
57 static const struct imxuart_platform_data uart_pdata __initconst = {
58 .flags = IMXUART_HAVE_RTSCTS,
61 static int uart_pins[] = {
68 static inline void __init mxc_init_imx_uart(void)
70 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins),
72 imx31_add_imx_uart0(&uart_pdata);
75 static struct resource dnet_resources[] = {
77 .name = "dnet-memory",
78 .start = QONG_DNET_BASEADDR,
79 .end = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
80 .flags = IORESOURCE_MEM,
82 .start = QONG_FPGA_IRQ,
84 .flags = IORESOURCE_IRQ,
88 static struct platform_device dnet_device = {
91 .num_resources = ARRAY_SIZE(dnet_resources),
92 .resource = dnet_resources,
95 static int __init qong_init_dnet(void)
99 ret = platform_device_register(&dnet_device);
105 static struct physmap_flash_data qong_flash_data = {
109 static struct resource qong_flash_resource = {
110 .start = MX31_CS0_BASE_ADDR,
111 .end = MX31_CS0_BASE_ADDR + SZ_128M - 1,
112 .flags = IORESOURCE_MEM,
115 static struct platform_device qong_nor_mtd_device = {
116 .name = "physmap-flash",
119 .platform_data = &qong_flash_data,
121 .resource = &qong_flash_resource,
125 static void qong_init_nor_mtd(void)
127 (void)platform_device_register(&qong_nor_mtd_device);
131 * Hardware specific access to control-lines
133 static void qong_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
135 struct nand_chip *nand_chip = mtd->priv;
137 if (cmd == NAND_CMD_NONE)
141 writeb(cmd, nand_chip->IO_ADDR_W + (1 << 24));
143 writeb(cmd, nand_chip->IO_ADDR_W + (1 << 23));
147 * Read the Device Ready pin.
149 static int qong_nand_device_ready(struct mtd_info *mtd)
151 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB));
154 static void qong_nand_select_chip(struct mtd_info *mtd, int chip)
157 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
159 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1);
162 static struct platform_nand_data qong_nand_data = {
169 .cmd_ctrl = qong_nand_cmd_ctrl,
170 .dev_ready = qong_nand_device_ready,
171 .select_chip = qong_nand_select_chip,
175 static struct resource qong_nand_resource = {
176 .start = MX31_CS3_BASE_ADDR,
177 .end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
178 .flags = IORESOURCE_MEM,
181 static struct platform_device qong_nand_device = {
185 .platform_data = &qong_nand_data,
188 .resource = &qong_nand_resource,
191 static void __init qong_init_nand_mtd(void)
194 mx31_setup_weimcs(3, 0x00004f00, 0x20013b31, 0x00020800);
195 mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
198 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO));
199 if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable"))
200 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
203 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO));
204 if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy"))
205 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB));
207 /* write protect pin */
208 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO));
209 if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp"))
210 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B));
212 platform_device_register(&qong_nand_device);
215 static void __init qong_init_fpga(void)
220 regs = ioremap(QONG_FPGA_CTRL_BASEADDR, QONG_FPGA_CTRL_SIZE);
222 printk(KERN_ERR "%s: failed to map registers, aborting.\n",
227 fpga_ver = readl(regs + QONG_FPGA_CTRL_VERSION);
229 printk(KERN_INFO "Qong FPGA version %d.%d.%d\n",
230 (fpga_ver & 0xF000) >> 12,
231 (fpga_ver & 0x0F00) >> 8, fpga_ver & 0x00FF);
232 if (fpga_ver < QONG_FPGA_VERSION(0, 8, 7)) {
233 printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based "
234 "devices won't be registered!\n");
238 /* register FPGA-based devices */
239 qong_init_nand_mtd();
244 * Board specific initialization.
246 static void __init qong_init(void)
253 static void __init qong_timer_init(void)
255 mx31_clocks_init(26000000);
258 static struct sys_timer qong_timer = {
259 .init = qong_timer_init,
262 MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
263 /* Maintainer: DENX Software Engineering GmbH */
264 .boot_params = MX3x_PHYS_OFFSET + 0x100,
265 .map_io = mx31_map_io,
266 .init_early = imx31_init_early,
267 .init_irq = mx31_init_irq,
268 .timer = &qong_timer,
269 .init_machine = qong_init,