2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/delay.h>
16 #include <linux/types.h>
17 #include <linux/init.h>
18 #include <linux/clk.h>
19 #include <linux/irq.h>
20 #include <linux/gpio.h>
21 #include <linux/smsc911x.h>
22 #include <linux/platform_device.h>
23 #include <linux/mfd/mc13783.h>
24 #include <linux/spi/spi.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/fsl_devices.h>
27 #include <linux/input/matrix_keypad.h>
29 #include <mach/hardware.h>
30 #include <asm/mach-types.h>
31 #include <asm/mach/arch.h>
32 #include <asm/mach/time.h>
33 #include <asm/memory.h>
34 #include <asm/mach/map.h>
35 #include <mach/common.h>
36 #include <mach/iomux-mx3.h>
38 #include "devices-imx31.h"
41 /* Definitions for components on the Debug board */
43 /* Base address of CPLD controller on the Debug board */
44 #define DEBUG_BASE_ADDRESS CS5_IO_ADDRESS(MX3x_CS5_BASE_ADDR)
46 /* LAN9217 ethernet base address */
47 #define LAN9217_BASE_ADDR MX3x_CS5_BASE_ADDR
49 /* CPLD config and interrupt base address */
50 #define CPLD_ADDR (DEBUG_BASE_ADDRESS + 0x20000)
52 /* status, interrupt */
53 #define CPLD_INT_STATUS_REG (CPLD_ADDR + 0x10)
54 #define CPLD_INT_MASK_REG (CPLD_ADDR + 0x38)
55 #define CPLD_INT_RESET_REG (CPLD_ADDR + 0x20)
56 /* magic word for debug CPLD */
57 #define CPLD_MAGIC_NUMBER1_REG (CPLD_ADDR + 0x40)
58 #define CPLD_MAGIC_NUMBER2_REG (CPLD_ADDR + 0x48)
59 /* CPLD code version */
60 #define CPLD_CODE_VER_REG (CPLD_ADDR + 0x50)
61 /* magic word for debug CPLD */
62 #define CPLD_MAGIC_NUMBER3_REG (CPLD_ADDR + 0x58)
64 /* CPLD IRQ line for external uart, external ethernet etc */
65 #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
67 #define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
68 #define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
70 #define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0)
72 #define MXC_MAX_EXP_IO_LINES 16
75 * This file contains the board-specific initialization routines.
78 static int mx31_3ds_pins[] = {
84 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
86 MX31_PIN_CSPI2_SCLK__SCLK,
87 MX31_PIN_CSPI2_MOSI__MOSI,
88 MX31_PIN_CSPI2_MISO__MISO,
89 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
90 MX31_PIN_CSPI2_SS0__SS0,
91 MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
93 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
95 IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
97 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
98 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
99 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
100 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
101 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
102 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
103 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
104 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
105 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
106 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
107 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
108 MX31_PIN_USBOTG_STP__USBOTG_STP,
110 MX31_PIN_KEY_ROW0_KEY_ROW0,
111 MX31_PIN_KEY_ROW1_KEY_ROW1,
112 MX31_PIN_KEY_ROW2_KEY_ROW2,
113 MX31_PIN_KEY_COL0_KEY_COL0,
114 MX31_PIN_KEY_COL1_KEY_COL1,
115 MX31_PIN_KEY_COL2_KEY_COL2,
116 MX31_PIN_KEY_COL3_KEY_COL3,
123 static const uint32_t mx31_3ds_keymap[] = {
126 KEY(1, 0, KEY_RIGHT),
128 KEY(1, 2, KEY_ENTER),
135 static struct matrix_keymap_data mx31_3ds_keymap_data = {
136 .keymap = mx31_3ds_keymap,
137 .keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
141 static struct regulator_init_data pwgtx_init = {
148 static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
150 .id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */
151 .init_data = &pwgtx_init,
153 .id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */
154 .init_data = &pwgtx_init,
159 static struct mc13783_platform_data mc13783_pdata __initdata = {
160 .regulators = mx31_3ds_regulators,
161 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
162 .flags = MC13783_USE_REGULATOR,
166 static int spi1_internal_chipselect[] = {
171 static const struct spi_imx_master spi1_pdata __initconst = {
172 .chipselect = spi1_internal_chipselect,
173 .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
176 static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
178 .modalias = "mc13783",
179 .max_speed_hz = 1000000,
181 .chip_select = 1, /* SS2 */
182 .platform_data = &mc13783_pdata,
183 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
191 static const struct mxc_nand_platform_data
192 mx31_3ds_nand_board_info __initconst = {
195 #ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
204 #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
205 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
207 #define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
209 static void mx31_3ds_usbotg_init(void)
211 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
212 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
213 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
214 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
215 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
216 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
217 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
218 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
219 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
220 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
221 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
222 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
224 gpio_request(USBOTG_RST_B, "otgusb-reset");
225 gpio_direction_output(USBOTG_RST_B, 0);
227 gpio_set_value(USBOTG_RST_B, 1);
230 static struct fsl_usb2_platform_data usbotg_pdata = {
231 .operating_mode = FSL_USB2_DR_DEVICE,
232 .phy_mode = FSL_USB2_PHY_ULPI,
235 static const struct imxuart_platform_data uart_pdata __initconst = {
236 .flags = IMXUART_HAVE_RTSCTS,
240 * Support for the SMSC9217 on the Debug board.
243 static struct smsc911x_platform_config smsc911x_config = {
244 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
245 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
246 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
247 .phy_interface = PHY_INTERFACE_MODE_MII,
250 static struct resource smsc911x_resources[] = {
252 .start = LAN9217_BASE_ADDR,
253 .end = LAN9217_BASE_ADDR + 0xff,
254 .flags = IORESOURCE_MEM,
256 .start = EXPIO_INT_ENET,
257 .end = EXPIO_INT_ENET,
258 .flags = IORESOURCE_IRQ,
262 static struct platform_device smsc911x_device = {
265 .num_resources = ARRAY_SIZE(smsc911x_resources),
266 .resource = smsc911x_resources,
268 .platform_data = &smsc911x_config,
273 * Routines for the CPLD on the debug board. It contains a CPLD handling
274 * LEDs, switches, interrupts for Ethernet.
277 static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
283 imr_val = __raw_readw(CPLD_INT_MASK_REG);
284 int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
286 expio_irq = MXC_EXP_IO_BASE;
287 for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
288 if ((int_valid & 1) == 0)
290 generic_handle_irq(expio_irq);
295 * Disable an expio pin's interrupt by setting the bit in the imr.
296 * @param irq an expio virtual irq number
298 static void expio_mask_irq(uint32_t irq)
301 uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
303 /* mask the interrupt */
304 reg = __raw_readw(CPLD_INT_MASK_REG);
306 __raw_writew(reg, CPLD_INT_MASK_REG);
310 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
311 * @param irq an expanded io virtual irq number
313 static void expio_ack_irq(uint32_t irq)
315 uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
317 /* clear the interrupt status */
318 __raw_writew(1 << expio, CPLD_INT_RESET_REG);
319 __raw_writew(0, CPLD_INT_RESET_REG);
320 /* mask the interrupt */
325 * Enable a expio pin's interrupt by clearing the bit in the imr.
326 * @param irq a expio virtual irq number
328 static void expio_unmask_irq(uint32_t irq)
331 uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
333 /* unmask the interrupt */
334 reg = __raw_readw(CPLD_INT_MASK_REG);
335 reg &= ~(1 << expio);
336 __raw_writew(reg, CPLD_INT_MASK_REG);
339 static struct irq_chip expio_irq_chip = {
340 .ack = expio_ack_irq,
341 .mask = expio_mask_irq,
342 .unmask = expio_unmask_irq,
345 static int __init mx31_3ds_init_expio(void)
350 /* Check if there's a debug board connected */
351 if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
352 (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
353 (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
354 /* No Debug board found */
358 pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
359 __raw_readw(CPLD_CODE_VER_REG));
362 * Configure INT line as GPIO input
364 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
366 pr_warning("could not get LAN irq gpio\n");
368 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
370 /* Disable the interrupts and clear the status */
371 __raw_writew(0, CPLD_INT_MASK_REG);
372 __raw_writew(0xFFFF, CPLD_INT_RESET_REG);
373 __raw_writew(0, CPLD_INT_RESET_REG);
374 __raw_writew(0x1F, CPLD_INT_MASK_REG);
375 for (i = MXC_EXP_IO_BASE;
376 i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
378 set_irq_chip(i, &expio_irq_chip);
379 set_irq_handler(i, handle_level_irq);
380 set_irq_flags(i, IRQF_VALID);
382 set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
383 set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
389 * This structure defines the MX31 memory map.
391 static struct map_desc mx31_3ds_io_desc[] __initdata = {
393 .virtual = MX31_CS5_BASE_ADDR_VIRT,
394 .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
395 .length = MX31_CS5_SIZE,
401 * Set up static virtual mappings.
403 static void __init mx31_3ds_map_io(void)
406 iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
410 * Board specific initialization.
412 static void __init mxc_board_init(void)
414 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
417 imx31_add_imx_uart0(&uart_pdata);
418 imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
420 imx31_add_spi_imx0(&spi1_pdata);
421 spi_register_board_info(mx31_3ds_spi_devs,
422 ARRAY_SIZE(mx31_3ds_spi_devs));
424 mxc_register_device(&imx_kpp_device, &mx31_3ds_keymap_data);
426 mx31_3ds_usbotg_init();
427 mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
429 if (!mx31_3ds_init_expio())
430 platform_device_register(&smsc911x_device);
433 static void __init mx31_3ds_timer_init(void)
435 mx31_clocks_init(26000000);
438 static struct sys_timer mx31_3ds_timer = {
439 .init = mx31_3ds_timer_init,
443 * The following uses standard kernel macros defined in arch.h in order to
444 * initialize __mach_desc_MX31_3DS data structure.
446 MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
447 /* Maintainer: Freescale Semiconductor, Inc. */
448 .phys_io = MX31_AIPS1_BASE_ADDR,
449 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
450 .boot_params = MX3x_PHYS_OFFSET + 0x100,
451 .map_io = mx31_3ds_map_io,
452 .init_irq = mx31_init_irq,
453 .init_machine = mxc_board_init,
454 .timer = &mx31_3ds_timer,