2 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
17 * Boston, MA 02110-1301, USA.
20 #include <linux/dma-mapping.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/serial.h>
24 #include <linux/gpio.h>
25 #include <mach/hardware.h>
26 #include <mach/irqs.h>
27 #include <mach/common.h>
28 #include <mach/mx3_camera.h>
32 /* GPIO port description */
33 static struct mxc_gpio_port imx_gpio_ports[] = {
35 .chip.label = "gpio-0",
36 .base = IO_ADDRESS(GPIO1_BASE_ADDR),
38 .virtual_irq_start = MXC_GPIO_IRQ_START,
40 .chip.label = "gpio-1",
41 .base = IO_ADDRESS(GPIO2_BASE_ADDR),
43 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
45 .chip.label = "gpio-2",
46 .base = IO_ADDRESS(GPIO3_BASE_ADDR),
48 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
52 int __init imx3x_register_gpios(void)
54 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
57 static struct resource mxc_w1_master_resources[] = {
59 .start = OWIRE_BASE_ADDR,
60 .end = OWIRE_BASE_ADDR + SZ_4K - 1,
61 .flags = IORESOURCE_MEM,
65 struct platform_device mxc_w1_master_device = {
68 .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
69 .resource = mxc_w1_master_resources,
72 #ifdef CONFIG_ARCH_MX31
73 static struct resource mxcsdhc0_resources[] = {
75 .start = MMC_SDHC1_BASE_ADDR,
76 .end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
77 .flags = IORESOURCE_MEM,
79 .start = MXC_INT_MMC_SDHC1,
80 .end = MXC_INT_MMC_SDHC1,
81 .flags = IORESOURCE_IRQ,
85 static struct resource mxcsdhc1_resources[] = {
87 .start = MMC_SDHC2_BASE_ADDR,
88 .end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
89 .flags = IORESOURCE_MEM,
91 .start = MXC_INT_MMC_SDHC2,
92 .end = MXC_INT_MMC_SDHC2,
93 .flags = IORESOURCE_IRQ,
97 struct platform_device mxcsdhc_device0 = {
100 .num_resources = ARRAY_SIZE(mxcsdhc0_resources),
101 .resource = mxcsdhc0_resources,
104 struct platform_device mxcsdhc_device1 = {
107 .num_resources = ARRAY_SIZE(mxcsdhc1_resources),
108 .resource = mxcsdhc1_resources,
111 static struct resource rnga_resources[] = {
113 .start = RNGA_BASE_ADDR,
114 .end = RNGA_BASE_ADDR + 0x28,
115 .flags = IORESOURCE_MEM,
119 struct platform_device mxc_rnga_device = {
123 .resource = rnga_resources,
125 #endif /* CONFIG_ARCH_MX31 */
127 /* i.MX31 Image Processing Unit */
129 /* The resource order is important! */
130 static struct resource mx3_ipu_rsrc[] = {
132 .start = IPU_CTRL_BASE_ADDR,
133 .end = IPU_CTRL_BASE_ADDR + 0x5F,
134 .flags = IORESOURCE_MEM,
136 .start = IPU_CTRL_BASE_ADDR + 0x88,
137 .end = IPU_CTRL_BASE_ADDR + 0xB3,
138 .flags = IORESOURCE_MEM,
140 .start = MXC_INT_IPU_SYN,
141 .end = MXC_INT_IPU_SYN,
142 .flags = IORESOURCE_IRQ,
144 .start = MXC_INT_IPU_ERR,
145 .end = MXC_INT_IPU_ERR,
146 .flags = IORESOURCE_IRQ,
150 struct platform_device mx3_ipu = {
153 .num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
154 .resource = mx3_ipu_rsrc,
157 static struct resource fb_resources[] = {
159 .start = IPU_CTRL_BASE_ADDR + 0xB4,
160 .end = IPU_CTRL_BASE_ADDR + 0x1BF,
161 .flags = IORESOURCE_MEM,
165 struct platform_device mx3_fb = {
166 .name = "mx3_sdc_fb",
168 .num_resources = ARRAY_SIZE(fb_resources),
169 .resource = fb_resources,
171 .coherent_dma_mask = DMA_BIT_MASK(32),
175 static struct resource camera_resources[] = {
177 .start = IPU_CTRL_BASE_ADDR + 0x60,
178 .end = IPU_CTRL_BASE_ADDR + 0x87,
179 .flags = IORESOURCE_MEM,
183 struct platform_device mx3_camera = {
184 .name = "mx3-camera",
186 .num_resources = ARRAY_SIZE(camera_resources),
187 .resource = camera_resources,
189 .coherent_dma_mask = DMA_BIT_MASK(32),
193 static struct resource otg_resources[] = {
195 .start = MX31_OTG_BASE_ADDR,
196 .end = MX31_OTG_BASE_ADDR + 0x1ff,
197 .flags = IORESOURCE_MEM,
199 .start = MXC_INT_USB3,
201 .flags = IORESOURCE_IRQ,
205 static u64 otg_dmamask = DMA_BIT_MASK(32);
207 /* OTG gadget device */
208 struct platform_device mxc_otg_udc_device = {
209 .name = "fsl-usb2-udc",
212 .dma_mask = &otg_dmamask,
213 .coherent_dma_mask = DMA_BIT_MASK(32),
215 .resource = otg_resources,
216 .num_resources = ARRAY_SIZE(otg_resources),
220 struct platform_device mxc_otg_host = {
224 .coherent_dma_mask = 0xffffffff,
225 .dma_mask = &otg_dmamask,
227 .resource = otg_resources,
228 .num_resources = ARRAY_SIZE(otg_resources),
233 static u64 usbh1_dmamask = ~(u32)0;
235 static struct resource mxc_usbh1_resources[] = {
237 .start = MX31_OTG_BASE_ADDR + 0x200,
238 .end = MX31_OTG_BASE_ADDR + 0x3ff,
239 .flags = IORESOURCE_MEM,
241 .start = MXC_INT_USB1,
243 .flags = IORESOURCE_IRQ,
247 struct platform_device mxc_usbh1 = {
251 .coherent_dma_mask = 0xffffffff,
252 .dma_mask = &usbh1_dmamask,
254 .resource = mxc_usbh1_resources,
255 .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
259 static u64 usbh2_dmamask = ~(u32)0;
261 static struct resource mxc_usbh2_resources[] = {
263 .start = MX31_OTG_BASE_ADDR + 0x400,
264 .end = MX31_OTG_BASE_ADDR + 0x5ff,
265 .flags = IORESOURCE_MEM,
267 .start = MXC_INT_USB2,
269 .flags = IORESOURCE_IRQ,
273 struct platform_device mxc_usbh2 = {
277 .coherent_dma_mask = 0xffffffff,
278 .dma_mask = &usbh2_dmamask,
280 .resource = mxc_usbh2_resources,
281 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
284 #if defined(CONFIG_ARCH_MX35)
285 static struct resource mxc_fec_resources[] = {
287 .start = MXC_FEC_BASE_ADDR,
288 .end = MXC_FEC_BASE_ADDR + 0xfff,
289 .flags = IORESOURCE_MEM,
291 .start = MXC_INT_FEC,
293 .flags = IORESOURCE_IRQ,
297 struct platform_device mxc_fec_device = {
300 .num_resources = ARRAY_SIZE(mxc_fec_resources),
301 .resource = mxc_fec_resources,
305 static struct resource imx_ssi_resources0[] = {
307 .start = SSI1_BASE_ADDR,
308 .end = SSI1_BASE_ADDR + 0xfff,
309 .flags = IORESOURCE_MEM,
311 .start = MX31_INT_SSI1,
312 .end = MX31_INT_SSI1,
313 .flags = IORESOURCE_IRQ,
317 static struct resource imx_ssi_resources1[] = {
319 .start = SSI2_BASE_ADDR,
320 .end = SSI2_BASE_ADDR + 0xfff,
321 .flags = IORESOURCE_MEM
323 .start = MX31_INT_SSI2,
324 .end = MX31_INT_SSI2,
325 .flags = IORESOURCE_IRQ,
329 struct platform_device imx_ssi_device0 = {
332 .num_resources = ARRAY_SIZE(imx_ssi_resources0),
333 .resource = imx_ssi_resources0,
336 struct platform_device imx_ssi_device1 = {
339 .num_resources = ARRAY_SIZE(imx_ssi_resources1),
340 .resource = imx_ssi_resources1,
343 static struct resource imx_wdt_resources[] = {
345 .flags = IORESOURCE_MEM,
349 struct platform_device imx_wdt_device0 = {
352 .num_resources = ARRAY_SIZE(imx_wdt_resources),
353 .resource = imx_wdt_resources,
356 static struct resource imx_rtc_resources[] = {
358 .start = MX31_RTC_BASE_ADDR,
359 .end = MX31_RTC_BASE_ADDR + 0x3fff,
360 .flags = IORESOURCE_MEM,
363 .start = MX31_INT_RTC,
364 .flags = IORESOURCE_IRQ,
368 struct platform_device imx_rtc_device0 = {
371 .num_resources = ARRAY_SIZE(imx_rtc_resources),
372 .resource = imx_rtc_resources,
375 static struct resource imx_kpp_resources[] = {
377 .start = MX3x_KPP_BASE_ADDR,
378 .end = MX3x_KPP_BASE_ADDR + 0xf,
379 .flags = IORESOURCE_MEM
381 .start = MX3x_INT_KPP,
383 .flags = IORESOURCE_IRQ,
387 struct platform_device imx_kpp_device = {
388 .name = "imx-keypad",
390 .num_resources = ARRAY_SIZE(imx_kpp_resources),
391 .resource = imx_kpp_resources,
394 static int __init mx3_devices_init(void)
396 #if defined(CONFIG_ARCH_MX31)
398 imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
399 imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
400 mxc_register_device(&mxc_rnga_device, NULL);
403 #if defined(CONFIG_ARCH_MX35)
405 otg_resources[0].start = MX35_OTG_BASE_ADDR;
406 otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
407 otg_resources[1].start = MXC_INT_USBOTG;
408 otg_resources[1].end = MXC_INT_USBOTG;
409 mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
410 mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
411 mxc_usbh1_resources[1].start = MXC_INT_USBHS;
412 mxc_usbh1_resources[1].end = MXC_INT_USBHS;
413 imx_ssi_resources0[1].start = MX35_INT_SSI1;
414 imx_ssi_resources0[1].end = MX35_INT_SSI1;
415 imx_ssi_resources1[1].start = MX35_INT_SSI2;
416 imx_ssi_resources1[1].end = MX35_INT_SSI2;
417 imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
418 imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
425 subsys_initcall(mx3_devices_init);