arch/arm/mach-mx3/clock-imx31.c

   1 /*
   2  * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17  * MA 02110-1301, USA.
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/err.h>
  25 #include <linux/io.h>
  26 #include <linux/clkdev.h>
  27
  28 #include <asm/div64.h>
  29
  30 #include <mach/clock.h>
  31 #include <mach/hardware.h>
  32 #include <mach/mx31.h>
  33 #include <mach/common.h>
  34
  35 #include "crm_regs.h"
  36
  37 #define PRE_DIV_MIN_FREQ    10000000 /* Minimum Frequency after Predivider */
  38
  39 static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
  40 {
  41         u32 min_pre, temp_pre, old_err, err;
  42
  43         if (div >= 512) {
  44                 *pre = 8;
  45                 *post = 64;
  46         } else if (div >= 64) {
  47                 min_pre = (div - 1) / 64 + 1;
  48                 old_err = 8;
  49                 for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
  50                         err = div % temp_pre;
  51                         if (err == 0) {
  52                                 *pre = temp_pre;
  53                                 break;
  54                         }
  55                         err = temp_pre - err;
  56                         if (err < old_err) {
  57                                 old_err = err;
  58                                 *pre = temp_pre;
  59                         }
  60                 }
  61                 *post = (div + *pre - 1) / *pre;
  62         } else if (div <= 8) {
  63                 *pre = div;
  64                 *post = 1;
  65         } else {
  66                 *pre = 1;
  67                 *post = div;
  68         }
  69 }
  70
  71 static struct clk mcu_pll_clk;
  72 static struct clk serial_pll_clk;
  73 static struct clk ipg_clk;
  74 static struct clk ckih_clk;
  75
  76 static int cgr_enable(struct clk *clk)
  77 {
  78         u32 reg;
  79
  80         if (!clk->enable_reg)
  81                 return 0;
  82
  83         reg = __raw_readl(clk->enable_reg);
  84         reg |= 3 << clk->enable_shift;
  85         __raw_writel(reg, clk->enable_reg);
  86
  87         return 0;
  88 }
  89
  90 static void cgr_disable(struct clk *clk)
  91 {
  92         u32 reg;
  93
  94         if (!clk->enable_reg)
  95                 return;
  96
  97         reg = __raw_readl(clk->enable_reg);
  98         reg &= ~(3 << clk->enable_shift);
  99
 100         /* special case for EMI clock */
 101         if (clk->enable_reg == MXC_CCM_CGR2 && clk->enable_shift == 8)
 102                 reg |= (1 << clk->enable_shift);
 103
 104         __raw_writel(reg, clk->enable_reg);
 105 }
 106
 107 static unsigned long pll_ref_get_rate(void)
 108 {
 109         unsigned long ccmr;
 110         unsigned int prcs;
 111
 112         ccmr = __raw_readl(MXC_CCM_CCMR);
 113         prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
 114         if (prcs == 0x1)
 115                 return CKIL_CLK_FREQ * 1024;
 116         else
 117                 return clk_get_rate(&ckih_clk);
 118 }
 119
 120 static unsigned long usb_pll_get_rate(struct clk *clk)
 121 {
 122         unsigned long reg;
 123
 124         reg = __raw_readl(MXC_CCM_UPCTL);
 125
 126         return mxc_decode_pll(reg, pll_ref_get_rate());
 127 }
 128
 129 static unsigned long serial_pll_get_rate(struct clk *clk)
 130 {
 131         unsigned long reg;
 132
 133         reg = __raw_readl(MXC_CCM_SRPCTL);
 134
 135         return mxc_decode_pll(reg, pll_ref_get_rate());
 136 }
 137
 138 static unsigned long mcu_pll_get_rate(struct clk *clk)
 139 {
 140         unsigned long reg, ccmr;
 141
 142         ccmr = __raw_readl(MXC_CCM_CCMR);
 143
 144         if (!(ccmr & MXC_CCM_CCMR_MPE) || (ccmr & MXC_CCM_CCMR_MDS))
 145                 return clk_get_rate(&ckih_clk);
 146
 147         reg = __raw_readl(MXC_CCM_MPCTL);
 148
 149         return mxc_decode_pll(reg, pll_ref_get_rate());
 150 }
 151
 152 static int usb_pll_enable(struct clk *clk)
 153 {
 154         u32 reg;
 155
 156         reg = __raw_readl(MXC_CCM_CCMR);
 157         reg |= MXC_CCM_CCMR_UPE;
 158         __raw_writel(reg, MXC_CCM_CCMR);
 159
 160         /* No lock bit on MX31, so using max time from spec */
 161         udelay(80);
 162
 163         return 0;
 164 }
 165
 166 static void usb_pll_disable(struct clk *clk)
 167 {
 168         u32 reg;
 169
 170         reg = __raw_readl(MXC_CCM_CCMR);
 171         reg &= ~MXC_CCM_CCMR_UPE;
 172         __raw_writel(reg, MXC_CCM_CCMR);
 173 }
 174
 175 static int serial_pll_enable(struct clk *clk)
 176 {
 177         u32 reg;
 178
 179         reg = __raw_readl(MXC_CCM_CCMR);
 180         reg |= MXC_CCM_CCMR_SPE;
 181         __raw_writel(reg, MXC_CCM_CCMR);
 182
 183         /* No lock bit on MX31, so using max time from spec */
 184         udelay(80);
 185
 186         return 0;
 187 }
 188
 189 static void serial_pll_disable(struct clk *clk)
 190 {
 191         u32 reg;
 192
 193         reg = __raw_readl(MXC_CCM_CCMR);
 194         reg &= ~MXC_CCM_CCMR_SPE;
 195         __raw_writel(reg, MXC_CCM_CCMR);
 196 }
 197
 198 #define PDR0(mask, off) ((__raw_readl(MXC_CCM_PDR0) & mask) >> off)
 199 #define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off)
 200 #define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off)
 201
 202 static unsigned long mcu_main_get_rate(struct clk *clk)
 203 {
 204         u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);
 205
 206         if ((pmcr0 & MXC_CCM_PMCR0_DFSUP1) == MXC_CCM_PMCR0_DFSUP1_SPLL)
 207                 return clk_get_rate(&serial_pll_clk);
 208         else
 209                 return clk_get_rate(&mcu_pll_clk);
 210 }
 211
 212 static unsigned long ahb_get_rate(struct clk *clk)
 213 {
 214         unsigned long max_pdf;
 215
 216         max_pdf = PDR0(MXC_CCM_PDR0_MAX_PODF_MASK,
 217                        MXC_CCM_PDR0_MAX_PODF_OFFSET);
 218         return clk_get_rate(clk->parent) / (max_pdf + 1);
 219 }
 220
 221 static unsigned long ipg_get_rate(struct clk *clk)
 222 {
 223         unsigned long ipg_pdf;
 224
 225         ipg_pdf = PDR0(MXC_CCM_PDR0_IPG_PODF_MASK,
 226                        MXC_CCM_PDR0_IPG_PODF_OFFSET);
 227         return clk_get_rate(clk->parent) / (ipg_pdf + 1);
 228 }
 229
 230 static unsigned long nfc_get_rate(struct clk *clk)
 231 {
 232         unsigned long nfc_pdf;
 233
 234         nfc_pdf = PDR0(MXC_CCM_PDR0_NFC_PODF_MASK,
 235                        MXC_CCM_PDR0_NFC_PODF_OFFSET);
 236         return clk_get_rate(clk->parent) / (nfc_pdf + 1);
 237 }
 238
 239 static unsigned long hsp_get_rate(struct clk *clk)
 240 {
 241         unsigned long hsp_pdf;
 242
 243         hsp_pdf = PDR0(MXC_CCM_PDR0_HSP_PODF_MASK,
 244                        MXC_CCM_PDR0_HSP_PODF_OFFSET);
 245         return clk_get_rate(clk->parent) / (hsp_pdf + 1);
 246 }
 247
 248 static unsigned long usb_get_rate(struct clk *clk)
 249 {
 250         unsigned long usb_pdf, usb_prepdf;
 251
 252         usb_pdf = PDR1(MXC_CCM_PDR1_USB_PODF_MASK,
 253                        MXC_CCM_PDR1_USB_PODF_OFFSET);
 254         usb_prepdf = PDR1(MXC_CCM_PDR1_USB_PRDF_MASK,
 255                           MXC_CCM_PDR1_USB_PRDF_OFFSET);
 256         return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1);
 257 }
 258
 259 static unsigned long csi_get_rate(struct clk *clk)
 260 {
 261         u32 reg, pre, post;
 262
 263         reg = __raw_readl(MXC_CCM_PDR0);
 264         pre = (reg & MXC_CCM_PDR0_CSI_PRDF_MASK) >>
 265             MXC_CCM_PDR0_CSI_PRDF_OFFSET;
 266         pre++;
 267         post = (reg & MXC_CCM_PDR0_CSI_PODF_MASK) >>
 268             MXC_CCM_PDR0_CSI_PODF_OFFSET;
 269         post++;
 270         return clk_get_rate(clk->parent) / (pre * post);
 271 }
 272
 273 static unsigned long csi_round_rate(struct clk *clk, unsigned long rate)
 274 {
 275         u32 pre, post, parent = clk_get_rate(clk->parent);
 276         u32 div = parent / rate;
 277
 278         if (parent % rate)
 279                 div++;
 280
 281         __calc_pre_post_dividers(div, &pre, &post);
 282
 283         return parent / (pre * post);
 284 }
 285
 286 static int csi_set_rate(struct clk *clk, unsigned long rate)
 287 {
 288         u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
 289
 290         div = parent / rate;
 291
 292         if ((parent / div) != rate)
 293                 return -EINVAL;
 294
 295         __calc_pre_post_dividers(div, &pre, &post);
 296
 297         /* Set CSI clock divider */
 298         reg = __raw_readl(MXC_CCM_PDR0) &
 299             ~(MXC_CCM_PDR0_CSI_PODF_MASK | MXC_CCM_PDR0_CSI_PRDF_MASK);
 300         reg |= (post - 1) << MXC_CCM_PDR0_CSI_PODF_OFFSET;
 301         reg |= (pre - 1) << MXC_CCM_PDR0_CSI_PRDF_OFFSET;
 302         __raw_writel(reg, MXC_CCM_PDR0);
 303
 304         return 0;
 305 }
 306
 307 static unsigned long ssi1_get_rate(struct clk *clk)
 308 {
 309         unsigned long ssi1_pdf, ssi1_prepdf;
 310
 311         ssi1_pdf = PDR1(MXC_CCM_PDR1_SSI1_PODF_MASK,
 312                         MXC_CCM_PDR1_SSI1_PODF_OFFSET);
 313         ssi1_prepdf = PDR1(MXC_CCM_PDR1_SSI1_PRE_PODF_MASK,
 314                            MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET);
 315         return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1);
 316 }
 317
 318 static unsigned long ssi2_get_rate(struct clk *clk)
 319 {
 320         unsigned long ssi2_pdf, ssi2_prepdf;
 321
 322         ssi2_pdf = PDR1(MXC_CCM_PDR1_SSI2_PODF_MASK,
 323                         MXC_CCM_PDR1_SSI2_PODF_OFFSET);
 324         ssi2_prepdf = PDR1(MXC_CCM_PDR1_SSI2_PRE_PODF_MASK,
 325                            MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET);
 326         return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1);
 327 }
 328
 329 static unsigned long firi_get_rate(struct clk *clk)
 330 {
 331         unsigned long firi_pdf, firi_prepdf;
 332
 333         firi_pdf = PDR1(MXC_CCM_PDR1_FIRI_PODF_MASK,
 334                         MXC_CCM_PDR1_FIRI_PODF_OFFSET);
 335         firi_prepdf = PDR1(MXC_CCM_PDR1_FIRI_PRE_PODF_MASK,
 336                            MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET);
 337         return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1);
 338 }
 339
 340 static unsigned long firi_round_rate(struct clk *clk, unsigned long rate)
 341 {
 342         u32 pre, post;
 343         u32 parent = clk_get_rate(clk->parent);
 344         u32 div = parent / rate;
 345
 346         if (parent % rate)
 347                 div++;
 348
 349         __calc_pre_post_dividers(div, &pre, &post);
 350
 351         return parent / (pre * post);
 352
 353 }
 354
 355 static int firi_set_rate(struct clk *clk, unsigned long rate)
 356 {
 357         u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
 358
 359         div = parent / rate;
 360
 361         if ((parent / div) != rate)
 362                 return -EINVAL;
 363
 364         __calc_pre_post_dividers(div, &pre, &post);
 365
 366         /* Set FIRI clock divider */
 367         reg = __raw_readl(MXC_CCM_PDR1) &
 368             ~(MXC_CCM_PDR1_FIRI_PODF_MASK | MXC_CCM_PDR1_FIRI_PRE_PODF_MASK);
 369         reg |= (pre - 1) << MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET;
 370         reg |= (post - 1) << MXC_CCM_PDR1_FIRI_PODF_OFFSET;
 371         __raw_writel(reg, MXC_CCM_PDR1);
 372
 373         return 0;
 374 }
 375
 376 static unsigned long mbx_get_rate(struct clk *clk)
 377 {
 378         return clk_get_rate(clk->parent) / 2;
 379 }
 380
 381 static unsigned long mstick1_get_rate(struct clk *clk)
 382 {
 383         unsigned long msti_pdf;
 384
 385         msti_pdf = PDR2(MXC_CCM_PDR2_MST1_PDF_MASK,
 386                         MXC_CCM_PDR2_MST1_PDF_OFFSET);
 387         return clk_get_rate(clk->parent) / (msti_pdf + 1);
 388 }
 389
 390 static unsigned long mstick2_get_rate(struct clk *clk)
 391 {
 392         unsigned long msti_pdf;
 393
 394         msti_pdf = PDR2(MXC_CCM_PDR2_MST2_PDF_MASK,
 395                         MXC_CCM_PDR2_MST2_PDF_OFFSET);
 396         return clk_get_rate(clk->parent) / (msti_pdf + 1);
 397 }
 398
 399 static unsigned long ckih_rate;
 400
 401 static unsigned long clk_ckih_get_rate(struct clk *clk)
 402 {
 403         return ckih_rate;
 404 }
 405
 406 static unsigned long clk_ckil_get_rate(struct clk *clk)
 407 {
 408         return CKIL_CLK_FREQ;
 409 }
 410
 411 static struct clk ckih_clk = {
 412         .get_rate = clk_ckih_get_rate,
 413 };
 414
 415 static struct clk mcu_pll_clk = {
 416         .parent = &ckih_clk,
 417         .get_rate = mcu_pll_get_rate,
 418 };
 419
 420 static struct clk mcu_main_clk = {
 421         .parent = &mcu_pll_clk,
 422         .get_rate = mcu_main_get_rate,
 423 };
 424
 425 static struct clk serial_pll_clk = {
 426         .parent = &ckih_clk,
 427         .get_rate = serial_pll_get_rate,
 428         .enable = serial_pll_enable,
 429         .disable = serial_pll_disable,
 430 };
 431
 432 static struct clk usb_pll_clk = {
 433         .parent = &ckih_clk,
 434         .get_rate = usb_pll_get_rate,
 435         .enable = usb_pll_enable,
 436         .disable = usb_pll_disable,
 437 };
 438
 439 static struct clk ahb_clk = {
 440         .parent = &mcu_main_clk,
 441         .get_rate = ahb_get_rate,
 442 };
 443
 444 #define DEFINE_CLOCK(name, i, er, es, gr, s, p)         \
 445         static struct clk name = {                      \
 446                 .id             = i,                    \
 447                 .enable_reg     = er,                   \
 448                 .enable_shift   = es,                   \
 449                 .get_rate       = gr,                   \
 450                 .enable         = cgr_enable,           \
 451                 .disable        = cgr_disable,          \
 452                 .secondary      = s,                    \
 453                 .parent         = p,                    \
 454         }
 455
 456 #define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p)       \
 457         static struct clk name = {                              \
 458                 .id             = i,                            \
 459                 .enable_reg     = er,                           \
 460                 .enable_shift   = es,                           \
 461                 .get_rate       = getsetround##_get_rate,       \
 462                 .set_rate       = getsetround##_set_rate,       \
 463                 .round_rate     = getsetround##_round_rate,     \
 464                 .enable         = cgr_enable,                   \
 465                 .disable        = cgr_disable,                  \
 466                 .secondary      = s,                            \
 467                 .parent         = p,                            \
 468         }
 469
 470 DEFINE_CLOCK(perclk_clk,  0, NULL,          0, NULL, NULL, &ipg_clk);
 471 DEFINE_CLOCK(ckil_clk,    0, NULL,          0, clk_ckil_get_rate, NULL, NULL);
 472
 473 DEFINE_CLOCK(sdhc1_clk,   0, MXC_CCM_CGR0,  0, NULL, NULL, &perclk_clk);
 474 DEFINE_CLOCK(sdhc2_clk,   1, MXC_CCM_CGR0,  2, NULL, NULL, &perclk_clk);
 475 DEFINE_CLOCK(gpt_clk,     0, MXC_CCM_CGR0,  4, NULL, NULL, &perclk_clk);
 476 DEFINE_CLOCK(epit1_clk,   0, MXC_CCM_CGR0,  6, NULL, NULL, &perclk_clk);
 477 DEFINE_CLOCK(epit2_clk,   1, MXC_CCM_CGR0,  8, NULL, NULL, &perclk_clk);
 478 DEFINE_CLOCK(iim_clk,     0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk);
 479 DEFINE_CLOCK(ata_clk,     0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk);
 480 DEFINE_CLOCK(sdma_clk1,   0, MXC_CCM_CGR0, 14, NULL, NULL, &ahb_clk);
 481 DEFINE_CLOCK(cspi3_clk,   2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk);
 482 DEFINE_CLOCK(rng_clk,     0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk);
 483 DEFINE_CLOCK(uart1_clk,   0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk);
 484 DEFINE_CLOCK(uart2_clk,   1, MXC_CCM_CGR0, 22, NULL, NULL, &perclk_clk);
 485 DEFINE_CLOCK(ssi1_clk,    0, MXC_CCM_CGR0, 24, ssi1_get_rate, NULL, &serial_pll_clk);
 486 DEFINE_CLOCK(i2c1_clk,    0, MXC_CCM_CGR0, 26, NULL, NULL, &perclk_clk);
 487 DEFINE_CLOCK(i2c2_clk,    1, MXC_CCM_CGR0, 28, NULL, NULL, &perclk_clk);
 488 DEFINE_CLOCK(i2c3_clk,    2, MXC_CCM_CGR0, 30, NULL, NULL, &perclk_clk);
 489
 490 DEFINE_CLOCK(mpeg4_clk,   0, MXC_CCM_CGR1,  0, NULL, NULL, &ahb_clk);
 491 DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1,  2, mstick1_get_rate, NULL, &usb_pll_clk);
 492 DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1,  4, mstick2_get_rate, NULL, &usb_pll_clk);
 493 DEFINE_CLOCK1(csi_clk,    0, MXC_CCM_CGR1,  6, csi, NULL, &serial_pll_clk);
 494 DEFINE_CLOCK(rtc_clk,     0, MXC_CCM_CGR1,  8, NULL, NULL, &ckil_clk);
 495 DEFINE_CLOCK(wdog_clk,    0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
 496 DEFINE_CLOCK(pwm_clk,     0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
 497 DEFINE_CLOCK(usb_clk2,    0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk);
 498 DEFINE_CLOCK(kpp_clk,     0, MXC_CCM_CGR1, 20, NULL, NULL, &ipg_clk);
 499 DEFINE_CLOCK(ipu_clk,     0, MXC_CCM_CGR1, 22, hsp_get_rate, NULL, &mcu_main_clk);
 500 DEFINE_CLOCK(uart3_clk,   2, MXC_CCM_CGR1, 24, NULL, NULL, &perclk_clk);
 501 DEFINE_CLOCK(uart4_clk,   3, MXC_CCM_CGR1, 26, NULL, NULL, &perclk_clk);
 502 DEFINE_CLOCK(uart5_clk,   4, MXC_CCM_CGR1, 28, NULL, NULL, &perclk_clk);
 503 DEFINE_CLOCK(owire_clk,   0, MXC_CCM_CGR1, 30, NULL, NULL, &perclk_clk);
 504
 505 DEFINE_CLOCK(ssi2_clk,    1, MXC_CCM_CGR2,  0, ssi2_get_rate, NULL, &serial_pll_clk);
 506 DEFINE_CLOCK(cspi1_clk,   0, MXC_CCM_CGR2,  2, NULL, NULL, &ipg_clk);
 507 DEFINE_CLOCK(cspi2_clk,   1, MXC_CCM_CGR2,  4, NULL, NULL, &ipg_clk);
 508 DEFINE_CLOCK(mbx_clk,     0, MXC_CCM_CGR2,  6, mbx_get_rate, NULL, &ahb_clk);
 509 DEFINE_CLOCK(emi_clk,     0, MXC_CCM_CGR2,  8, NULL, NULL, &ahb_clk);
 510 DEFINE_CLOCK(rtic_clk,    0, MXC_CCM_CGR2, 10, NULL, NULL, &ahb_clk);
 511 DEFINE_CLOCK1(firi_clk,   0, MXC_CCM_CGR2, 12, firi, NULL, &usb_pll_clk);
 512
 513 DEFINE_CLOCK(sdma_clk2,   0, NULL,          0, NULL, NULL, &ipg_clk);
 514 DEFINE_CLOCK(usb_clk1,    0, NULL,          0, usb_get_rate, NULL, &usb_pll_clk);
 515 DEFINE_CLOCK(nfc_clk,     0, NULL,          0, nfc_get_rate, NULL, &ahb_clk);
 516 DEFINE_CLOCK(scc_clk,     0, NULL,          0, NULL, NULL, &ipg_clk);
 517 DEFINE_CLOCK(ipg_clk,     0, NULL,          0, ipg_get_rate, NULL, &ahb_clk);
 518
 519 #define _REGISTER_CLOCK(d, n, c) \
 520         { \
 521                 .dev_id = d, \
 522                 .con_id = n, \
 523                 .clk = &c, \
 524         },
 525
 526 static struct clk_lookup lookups[] = {
 527         _REGISTER_CLOCK(NULL, "emi", emi_clk)
 528         _REGISTER_CLOCK("imx31-cspi.0", NULL, cspi1_clk)
 529         _REGISTER_CLOCK("imx31-cspi.1", NULL, cspi2_clk)
 530         _REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk)
 531         _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
 532         _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
 533         _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
 534         _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
 535         _REGISTER_CLOCK(NULL, "epit", epit1_clk)
 536         _REGISTER_CLOCK(NULL, "epit", epit2_clk)
 537         _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
 538         _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
 539         _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
 540         _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
 541         _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk1)
 542         _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk2)
 543         _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk1)
 544         _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk2)
 545         _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk1)
 546         _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk2)
 547         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1)
 548         _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2)
 549         _REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk)
 550         _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
 551         _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
 552         _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
 553         _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
 554         _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
 555         _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
 556         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
 557         _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
 558         _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
 559         _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
 560         _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
 561         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
 562         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
 563         _REGISTER_CLOCK(NULL, "firi", firi_clk)
 564         _REGISTER_CLOCK(NULL, "ata", ata_clk)
 565         _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
 566         _REGISTER_CLOCK(NULL, "rng", rng_clk)
 567         _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk1)
 568         _REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2)
 569         _REGISTER_CLOCK(NULL, "mstick", mstick1_clk)
 570         _REGISTER_CLOCK(NULL, "mstick", mstick2_clk)
 571         _REGISTER_CLOCK(NULL, "scc", scc_clk)
 572         _REGISTER_CLOCK(NULL, "iim", iim_clk)
 573         _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
 574         _REGISTER_CLOCK(NULL, "mbx", mbx_clk)
 575 };
 576
 577 int __init mx31_clocks_init(unsigned long fref)
 578 {
 579         u32 reg;
 580
 581         ckih_rate = fref;
 582
 583         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 584
 585         /* change the csi_clk parent if necessary */
 586         reg = __raw_readl(MXC_CCM_CCMR);
 587         if (!(reg & MXC_CCM_CCMR_CSCS))
 588                 if (clk_set_parent(&csi_clk, &usb_pll_clk))
 589                         pr_err("%s: error changing csi_clk parent\n", __func__);
 590
 591
 592         /* Turn off all possible clocks */
 593         __raw_writel((3 << 4), MXC_CCM_CGR0);
 594         __raw_writel(0, MXC_CCM_CGR1);
 595         __raw_writel((3 << 8) | (3 << 14) | (3 << 16)|
 596                      1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for
 597                                            MX32, but still required to be set */
 598                      MXC_CCM_CGR2);
 599
 600         /*
 601          * Before turning off usb_pll make sure ipg_per_clk is generated
 602          * by ipg_clk and not usb_pll.
 603          */
 604         __raw_writel(__raw_readl(MXC_CCM_CCMR) | (1 << 24), MXC_CCM_CCMR);
 605
 606         usb_pll_disable(&usb_pll_clk);
 607
 608         pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));
 609
 610         clk_enable(&gpt_clk);
 611         clk_enable(&emi_clk);
 612         clk_enable(&iim_clk);
 613
 614         clk_enable(&serial_pll_clk);
 615
 616         mx31_read_cpu_rev();
 617
 618         if (mx31_revision() >= IMX_CHIP_REVISION_2_0) {
 619                 reg = __raw_readl(MXC_CCM_PMCR1);
 620                 /* No PLL restart on DVFS switch; enable auto EMI handshake */
 621                 reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;
 622                 __raw_writel(reg, MXC_CCM_PMCR1);
 623         }
 624
 625         mxc_timer_init(&ipg_clk, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
 626                         MX31_INT_GPT);
 627
 628         return 0;
 629 }
 630