2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/platform_device.h>
22 #include <linux/mtd/mtd.h>
23 #include <linux/mtd/map.h>
24 #include <linux/mtd/partitions.h>
25 #include <linux/mtd/physmap.h>
26 #include <asm/arch/common.h>
27 #include <asm/hardware.h>
28 #include <asm/mach-types.h>
29 #include <asm/mach/arch.h>
30 #include <asm/mach/time.h>
31 #include <asm/mach/map.h>
32 #include <asm/arch/gpio.h>
33 #include <asm/arch/imx-uart.h>
34 #include <asm/arch/iomux-mx1-mx2.h>
35 #include <asm/arch/board-mx27ads.h>
38 static struct physmap_flash_data mx27ads_flash_data = {
42 static struct resource mx27ads_flash_resource = {
44 .end = 0xc0000000 + 0x02000000 - 1,
45 .flags = IORESOURCE_MEM,
49 static struct platform_device mx27ads_nor_mtd_device = {
50 .name = "physmap-flash",
53 .platform_data = &mx27ads_flash_data,
56 .resource = &mx27ads_flash_resource,
59 static int mxc_uart0_pins[] = {
66 static int uart_mxc_port0_init(struct platform_device *pdev)
68 return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
69 ARRAY_SIZE(mxc_uart0_pins),
70 MXC_GPIO_ALLOC_MODE_NORMAL, "UART0");
73 static int uart_mxc_port0_exit(struct platform_device *pdev)
75 return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
76 ARRAY_SIZE(mxc_uart0_pins),
77 MXC_GPIO_ALLOC_MODE_RELEASE, "UART0");
80 static int mxc_uart1_pins[] = {
87 static int uart_mxc_port1_init(struct platform_device *pdev)
89 return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
90 ARRAY_SIZE(mxc_uart1_pins),
91 MXC_GPIO_ALLOC_MODE_NORMAL, "UART1");
94 static int uart_mxc_port1_exit(struct platform_device *pdev)
96 return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
97 ARRAY_SIZE(mxc_uart1_pins),
98 MXC_GPIO_ALLOC_MODE_RELEASE, "UART1");
101 static int mxc_uart2_pins[] = {
108 static int uart_mxc_port2_init(struct platform_device *pdev)
110 return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
111 ARRAY_SIZE(mxc_uart2_pins),
112 MXC_GPIO_ALLOC_MODE_NORMAL, "UART2");
115 static int uart_mxc_port2_exit(struct platform_device *pdev)
117 return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
118 ARRAY_SIZE(mxc_uart2_pins),
119 MXC_GPIO_ALLOC_MODE_RELEASE, "UART2");
122 static int mxc_uart3_pins[] = {
129 static int uart_mxc_port3_init(struct platform_device *pdev)
131 return mxc_gpio_setup_multiple_pins(mxc_uart3_pins,
132 ARRAY_SIZE(mxc_uart3_pins),
133 MXC_GPIO_ALLOC_MODE_NORMAL, "UART3");
136 static int uart_mxc_port3_exit(struct platform_device *pdev)
138 return mxc_gpio_setup_multiple_pins(mxc_uart3_pins,
139 ARRAY_SIZE(mxc_uart3_pins),
140 MXC_GPIO_ALLOC_MODE_RELEASE, "UART3");
143 static int mxc_uart4_pins[] = {
150 static int uart_mxc_port4_init(struct platform_device *pdev)
152 return mxc_gpio_setup_multiple_pins(mxc_uart4_pins,
153 ARRAY_SIZE(mxc_uart4_pins),
154 MXC_GPIO_ALLOC_MODE_NORMAL, "UART4");
157 static int uart_mxc_port4_exit(struct platform_device *pdev)
159 return mxc_gpio_setup_multiple_pins(mxc_uart4_pins,
160 ARRAY_SIZE(mxc_uart4_pins),
161 MXC_GPIO_ALLOC_MODE_RELEASE, "UART4");
164 static int mxc_uart5_pins[] = {
171 static int uart_mxc_port5_init(struct platform_device *pdev)
173 return mxc_gpio_setup_multiple_pins(mxc_uart5_pins,
174 ARRAY_SIZE(mxc_uart5_pins),
175 MXC_GPIO_ALLOC_MODE_NORMAL, "UART5");
178 static int uart_mxc_port5_exit(struct platform_device *pdev)
180 return mxc_gpio_setup_multiple_pins(mxc_uart5_pins,
181 ARRAY_SIZE(mxc_uart5_pins),
182 MXC_GPIO_ALLOC_MODE_RELEASE, "UART5");
185 static struct platform_device *platform_devices[] __initdata = {
186 &mx27ads_nor_mtd_device,
189 static int mxc_fec_pins[] = {
201 PD11_AOUT_FEC_TX_CLK,
210 static void gpio_fec_active(void)
212 mxc_gpio_setup_multiple_pins(mxc_fec_pins,
213 ARRAY_SIZE(mxc_fec_pins),
214 MXC_GPIO_ALLOC_MODE_NORMAL, "FEC");
217 static void gpio_fec_inactive(void)
219 mxc_gpio_setup_multiple_pins(mxc_fec_pins,
220 ARRAY_SIZE(mxc_fec_pins),
221 MXC_GPIO_ALLOC_MODE_RELEASE, "FEC");
224 static struct imxuart_platform_data uart_pdata[] = {
226 .init = uart_mxc_port0_init,
227 .exit = uart_mxc_port0_exit,
228 .flags = IMXUART_HAVE_RTSCTS,
230 .init = uart_mxc_port1_init,
231 .exit = uart_mxc_port1_exit,
232 .flags = IMXUART_HAVE_RTSCTS,
234 .init = uart_mxc_port2_init,
235 .exit = uart_mxc_port2_exit,
236 .flags = IMXUART_HAVE_RTSCTS,
238 .init = uart_mxc_port3_init,
239 .exit = uart_mxc_port3_exit,
240 .flags = IMXUART_HAVE_RTSCTS,
242 .init = uart_mxc_port4_init,
243 .exit = uart_mxc_port4_exit,
244 .flags = IMXUART_HAVE_RTSCTS,
246 .init = uart_mxc_port5_init,
247 .exit = uart_mxc_port5_exit,
248 .flags = IMXUART_HAVE_RTSCTS,
252 static void __init mx27ads_board_init(void)
258 for (i = 0; i < 6; i++)
259 imx_init_uart(i, &uart_pdata[i]);
261 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
264 static void __init mx27ads_timer_init(void)
266 unsigned long fref = 26000000;
268 if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
271 mxc_clocks_init(fref);
272 mxc_timer_init("gpt_clk.0");
275 struct sys_timer mx27ads_timer = {
276 .init = mx27ads_timer_init,
279 static struct map_desc mx27ads_io_desc[] __initdata = {
281 .virtual = PBC_BASE_ADDRESS,
282 .pfn = __phys_to_pfn(CS4_BASE_ADDR),
288 void __init mx27ads_map_io(void)
291 iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
294 MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
295 /* maintainer: Freescale Semiconductor, Inc. */
296 .phys_io = AIPI_BASE_ADDR,
297 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
298 .boot_params = PHYS_OFFSET + 0x100,
299 .map_io = mx27ads_map_io,
300 .init_irq = mxc_init_irq,
301 .init_machine = mx27ads_board_init,
302 .timer = &mx27ads_timer,