arch/arm/mach-msm/timer.c

   1 /* linux/arch/arm/mach-msm/timer.c
   2  *
   3  * Copyright (C) 2007 Google, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/time.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/irq.h>
  20 #include <linux/clk.h>
  21 #include <linux/clockchips.h>
  22 #include <linux/delay.h>
  23 #include <linux/io.h>
  24
  25 #include <asm/mach/time.h>
  26 #include <asm/hardware/gic.h>
  27
  28 #include <mach/msm_iomap.h>
  29 #include <mach/cpu.h>
  30
  31 #define TIMER_MATCH_VAL         0x0000
  32 #define TIMER_COUNT_VAL         0x0004
  33 #define TIMER_ENABLE            0x0008
  34 #define TIMER_ENABLE_CLR_ON_MATCH_EN    2
  35 #define TIMER_ENABLE_EN                 1
  36 #define TIMER_CLEAR             0x000C
  37 #define DGT_CLK_CTL             0x0034
  38 enum {
  39         DGT_CLK_CTL_DIV_1 = 0,
  40         DGT_CLK_CTL_DIV_2 = 1,
  41         DGT_CLK_CTL_DIV_3 = 2,
  42         DGT_CLK_CTL_DIV_4 = 3,
  43 };
  44 #define CSR_PROTECTION          0x0020
  45 #define CSR_PROTECTION_EN               1
  46
  47 #define GPT_HZ 32768
  48
  49 enum timer_location {
  50         LOCAL_TIMER = 0,
  51         GLOBAL_TIMER = 1,
  52 };
  53
  54 #define MSM_GLOBAL_TIMER MSM_CLOCK_DGT
  55
  56 /* TODO: Remove these ifdefs */
  57 #if defined(CONFIG_ARCH_QSD8X50)
  58 #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
  59 #define MSM_DGT_SHIFT (0)
  60 #elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) || \
  61                                       defined(CONFIG_ARCH_MSM8960)
  62 #define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
  63 #define MSM_DGT_SHIFT (0)
  64 #else
  65 #define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */
  66 #define MSM_DGT_SHIFT (5)
  67 #endif
  68
  69 struct msm_clock {
  70         struct clock_event_device   clockevent;
  71         struct clocksource          clocksource;
  72         struct irqaction            irq;
  73         void __iomem                *regbase;
  74         uint32_t                    freq;
  75         uint32_t                    shift;
  76         void __iomem                *global_counter;
  77         void __iomem                *local_counter;
  78 };
  79
  80 enum {
  81         MSM_CLOCK_GPT,
  82         MSM_CLOCK_DGT,
  83         NR_TIMERS,
  84 };
  85
  86
  87 static struct msm_clock msm_clocks[];
  88 static struct clock_event_device *local_clock_event;
  89
  90 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
  91 {
  92         struct clock_event_device *evt = dev_id;
  93         if (smp_processor_id() != 0)
  94                 evt = local_clock_event;
  95         if (evt->event_handler == NULL)
  96                 return IRQ_HANDLED;
  97         evt->event_handler(evt);
  98         return IRQ_HANDLED;
  99 }
 100
 101 static cycle_t msm_read_timer_count(struct clocksource *cs)
 102 {
 103         struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource);
 104
 105         /*
 106          * Shift timer count down by a constant due to unreliable lower bits
 107          * on some targets.
 108          */
 109         return readl(clk->global_counter) >> clk->shift;
 110 }
 111
 112 static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt)
 113 {
 114 #ifdef CONFIG_SMP
 115         int i;
 116         for (i = 0; i < NR_TIMERS; i++)
 117                 if (evt == &(msm_clocks[i].clockevent))
 118                         return &msm_clocks[i];
 119         return &msm_clocks[MSM_GLOBAL_TIMER];
 120 #else
 121         return container_of(evt, struct msm_clock, clockevent);
 122 #endif
 123 }
 124
 125 static int msm_timer_set_next_event(unsigned long cycles,
 126                                     struct clock_event_device *evt)
 127 {
 128         struct msm_clock *clock = clockevent_to_clock(evt);
 129         uint32_t now = readl(clock->local_counter);
 130         uint32_t alarm = now + (cycles << clock->shift);
 131
 132         writel(alarm, clock->regbase + TIMER_MATCH_VAL);
 133         return 0;
 134 }
 135
 136 static void msm_timer_set_mode(enum clock_event_mode mode,
 137                               struct clock_event_device *evt)
 138 {
 139         struct msm_clock *clock = clockevent_to_clock(evt);
 140
 141         switch (mode) {
 142         case CLOCK_EVT_MODE_RESUME:
 143         case CLOCK_EVT_MODE_PERIODIC:
 144                 break;
 145         case CLOCK_EVT_MODE_ONESHOT:
 146                 writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
 147                 break;
 148         case CLOCK_EVT_MODE_UNUSED:
 149         case CLOCK_EVT_MODE_SHUTDOWN:
 150                 writel(0, clock->regbase + TIMER_ENABLE);
 151                 break;
 152         }
 153 }
 154
 155 static struct msm_clock msm_clocks[] = {
 156         [MSM_CLOCK_GPT] = {
 157                 .clockevent = {
 158                         .name           = "gp_timer",
 159                         .features       = CLOCK_EVT_FEAT_ONESHOT,
 160                         .shift          = 32,
 161                         .rating         = 200,
 162                         .set_next_event = msm_timer_set_next_event,
 163                         .set_mode       = msm_timer_set_mode,
 164                 },
 165                 .clocksource = {
 166                         .name           = "gp_timer",
 167                         .rating         = 200,
 168                         .read           = msm_read_timer_count,
 169                         .mask           = CLOCKSOURCE_MASK(32),
 170                         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 171                 },
 172                 .irq = {
 173                         .name    = "gp_timer",
 174                         .flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
 175                         .handler = msm_timer_interrupt,
 176                         .dev_id  = &msm_clocks[0].clockevent,
 177                         .irq     = INT_GP_TIMER_EXP
 178                 },
 179                 .freq = GPT_HZ,
 180         },
 181         [MSM_CLOCK_DGT] = {
 182                 .clockevent = {
 183                         .name           = "dg_timer",
 184                         .features       = CLOCK_EVT_FEAT_ONESHOT,
 185                         .shift          = 32 + MSM_DGT_SHIFT,
 186                         .rating         = 300,
 187                         .set_next_event = msm_timer_set_next_event,
 188                         .set_mode       = msm_timer_set_mode,
 189                 },
 190                 .clocksource = {
 191                         .name           = "dg_timer",
 192                         .rating         = 300,
 193                         .read           = msm_read_timer_count,
 194                         .mask           = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
 195                         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 196                 },
 197                 .irq = {
 198                         .name    = "dg_timer",
 199                         .flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
 200                         .handler = msm_timer_interrupt,
 201                         .dev_id  = &msm_clocks[1].clockevent,
 202                         .irq     = INT_DEBUG_TIMER_EXP
 203                 },
 204                 .freq = DGT_HZ >> MSM_DGT_SHIFT,
 205                 .shift = MSM_DGT_SHIFT,
 206         }
 207 };
 208
 209 static void __init msm_timer_init(void)
 210 {
 211         int i;
 212         int res;
 213         int global_offset = 0;
 214
 215         if (cpu_is_msm7x01()) {
 216                 msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
 217                 msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
 218         } else if (cpu_is_msm7x30()) {
 219                 msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
 220                 msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
 221         } else if (cpu_is_qsd8x50()) {
 222                 msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
 223                 msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
 224         } else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
 225                 msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
 226                 msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
 227
 228                 /* Use CPU0's timer as the global timer. */
 229                 global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
 230         } else
 231                 BUG();
 232
 233 #ifdef CONFIG_ARCH_MSM_SCORPIONMP
 234         writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
 235 #endif
 236
 237         for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
 238                 struct msm_clock *clock = &msm_clocks[i];
 239                 struct clock_event_device *ce = &clock->clockevent;
 240                 struct clocksource *cs = &clock->clocksource;
 241
 242                 clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
 243                 clock->global_counter = clock->local_counter + global_offset;
 244
 245                 writel(0, clock->regbase + TIMER_ENABLE);
 246                 writel(0, clock->regbase + TIMER_CLEAR);
 247                 writel(~0, clock->regbase + TIMER_MATCH_VAL);
 248
 249                 ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
 250                 /* allow at least 10 seconds to notice that the timer wrapped */
 251                 ce->max_delta_ns =
 252                         clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
 253                 /* 4 gets rounded down to 3 */
 254                 ce->min_delta_ns = clockevent_delta2ns(4, ce);
 255                 ce->cpumask = cpumask_of(0);
 256
 257                 res = clocksource_register_hz(cs, clock->freq);
 258                 if (res)
 259                         printk(KERN_ERR "msm_timer_init: clocksource_register "
 260                                "failed for %s\n", cs->name);
 261
 262                 res = setup_irq(clock->irq.irq, &clock->irq);
 263                 if (res)
 264                         printk(KERN_ERR "msm_timer_init: setup_irq "
 265                                "failed for %s\n", cs->name);
 266
 267                 clockevents_register_device(ce);
 268         }
 269 }
 270
 271 #ifdef CONFIG_SMP
 272 int __cpuinit local_timer_setup(struct clock_event_device *evt)
 273 {
 274         struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
 275
 276         /* Use existing clock_event for cpu 0 */
 277         if (!smp_processor_id())
 278                 return 0;
 279
 280         writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
 281
 282         if (!local_clock_event) {
 283                 writel(0, clock->regbase  + TIMER_ENABLE);
 284                 writel(0, clock->regbase + TIMER_CLEAR);
 285                 writel(~0, clock->regbase + TIMER_MATCH_VAL);
 286         }
 287         evt->irq = clock->irq.irq;
 288         evt->name = "local_timer";
 289         evt->features = CLOCK_EVT_FEAT_ONESHOT;
 290         evt->rating = clock->clockevent.rating;
 291         evt->set_mode = msm_timer_set_mode;
 292         evt->set_next_event = msm_timer_set_next_event;
 293         evt->shift = clock->clockevent.shift;
 294         evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift);
 295         evt->max_delta_ns =
 296                 clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
 297         evt->min_delta_ns = clockevent_delta2ns(4, evt);
 298
 299         local_clock_event = evt;
 300
 301         gic_enable_ppi(clock->irq.irq);
 302
 303         clockevents_register_device(evt);
 304         return 0;
 305 }
 306
 307 inline int local_timer_ack(void)
 308 {
 309         return 1;
 310 }
 311
 312 #endif
 313
 314 struct sys_timer msm_timer = {
 315         .init = msm_timer_init
 316 };