1 /* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of Code Aurora Forum, Inc. nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #ifndef __ASM_ARCH_MSM_IRQS_8XXX_H
31 #define __ASM_ARCH_MSM_IRQS_8XXX_H
33 /* MSM ACPU Interrupt Numbers */
35 #define INT_A9_M2A_0 0
36 #define INT_A9_M2A_1 1
37 #define INT_A9_M2A_2 2
38 #define INT_A9_M2A_3 3
39 #define INT_A9_M2A_4 4
40 #define INT_A9_M2A_5 5
41 #define INT_A9_M2A_6 6
42 #define INT_GP_TIMER_EXP 7
43 #define INT_DEBUG_TIMER_EXP 8
49 #define INT_AD6_EXT_VFR 14
50 #define INT_USB_OTG 15
51 #define INT_MDDI_PRI 16
52 #define INT_MDDI_EXT 17
53 #define INT_MDDI_CLIENT 18
55 #define INT_GRAPHICS 20
56 #define INT_ADM_AARM 21
57 #define INT_ADSP_A11 22
58 #define INT_ADSP_A9_A11 23
63 #define INT_KEYSENSE 28
64 #define INT_TCHSCRN_SSBI 29
65 #define INT_TCHSCRN1 30
66 #define INT_TCHSCRN2 31
68 #define INT_TCSR_MPRPH_SC1 (32 + 0)
69 #define INT_USB_FS2 (32 + 1)
70 #define INT_PWB_I2C (32 + 2)
71 #define INT_SOFTRESET (32 + 3)
72 #define INT_NAND_WR_ER_DONE (32 + 4)
73 #define INT_NAND_OP_DONE (32 + 5)
74 #define INT_TCSR_MPRPH_SC2 (32 + 6)
75 #define INT_OP_PEN (32 + 7)
76 #define INT_AD_HSSD (32 + 8)
77 #define INT_ARM11_PM (32 + 9)
78 #define INT_SDMA_NON_SECURE (32 + 10)
79 #define INT_TSIF_IRQ (32 + 11)
80 #define INT_UART1DM_IRQ (32 + 12)
81 #define INT_UART1DM_RX (32 + 13)
82 #define INT_SDMA_SECURE (32 + 14)
83 #define INT_SI2S_SLAVE (32 + 15)
84 #define INT_SC_I2CPU (32 + 16)
85 #define INT_SC_DBG_RDTRFULL (32 + 17)
86 #define INT_SC_DBG_WDTRFULL (32 + 18)
87 #define INT_SCPLL_CTL_DONE (32 + 19)
88 #define INT_UART2DM_IRQ (32 + 20)
89 #define INT_UART2DM_RX (32 + 21)
90 #define INT_VDC_MEC (32 + 22)
91 #define INT_VDC_DB (32 + 23)
92 #define INT_VDC_AXI (32 + 24)
93 #define INT_VFE (32 + 25)
94 #define INT_USB_HS (32 + 26)
95 #define INT_AUDIO_OUT0 (32 + 27)
96 #define INT_AUDIO_OUT1 (32 + 28)
97 #define INT_CRYPTO (32 + 29)
98 #define INT_AD6M_IDLE (32 + 30)
99 #define INT_SIRC_1 (32 + 31)
101 #define NR_GPIO_IRQS 165
102 #define NR_MSM_IRQS 64
103 #define NR_BOARD_IRQS 64