1 /* linux/arch/arm/mach-msm/gpio.c
3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/bitops.h>
18 #include <linux/gpio.h>
19 #include <linux/interrupt.h>
21 #include <linux/irq.h>
22 #include <linux/module.h>
26 #define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0)
28 #define MSM_GPIO_BANK(bank, first, last) \
31 .out = MSM_GPIO_OUT_##bank, \
32 .in = MSM_GPIO_IN_##bank, \
33 .int_status = MSM_GPIO_INT_STATUS_##bank, \
34 .int_clear = MSM_GPIO_INT_CLEAR_##bank, \
35 .int_en = MSM_GPIO_INT_EN_##bank, \
36 .int_edge = MSM_GPIO_INT_EDGE_##bank, \
37 .int_pos = MSM_GPIO_INT_POS_##bank, \
38 .oe = MSM_GPIO_OE_##bank, \
42 .ngpio = (last) - (first) + 1, \
43 .get = msm_gpio_get, \
44 .set = msm_gpio_set, \
45 .direction_input = msm_gpio_direction_input, \
46 .direction_output = msm_gpio_direction_output, \
47 .to_irq = msm_gpio_to_irq, \
48 .request = msm_gpio_request, \
49 .free = msm_gpio_free, \
53 #define MSM_GPIO_BROKEN_INT_CLEAR 1
55 struct msm_gpio_regs {
58 void __iomem *int_status;
59 void __iomem *int_clear;
61 void __iomem *int_edge;
62 void __iomem *int_pos;
66 struct msm_gpio_chip {
68 struct gpio_chip chip;
69 struct msm_gpio_regs regs;
70 #if MSM_GPIO_BROKEN_INT_CLEAR
71 unsigned int_status_copy;
73 unsigned int both_edge_detect;
74 unsigned int int_enable[2]; /* 0: awake, 1: sleep */
77 static int msm_gpio_write(struct msm_gpio_chip *msm_chip,
78 unsigned offset, unsigned on)
80 unsigned mask = BIT(offset);
83 val = readl(msm_chip->regs.out);
85 writel(val | mask, msm_chip->regs.out);
87 writel(val & ~mask, msm_chip->regs.out);
91 static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip)
94 unsigned pol, val, val2, intstat;
96 val = readl(msm_chip->regs.in);
97 pol = readl(msm_chip->regs.int_pos);
98 pol = (pol & ~msm_chip->both_edge_detect) |
99 (~val & msm_chip->both_edge_detect);
100 writel(pol, msm_chip->regs.int_pos);
101 intstat = readl(msm_chip->regs.int_status);
102 val2 = readl(msm_chip->regs.in);
103 if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0)
105 } while (loop_limit-- > 0);
106 printk(KERN_ERR "msm_gpio_update_both_edge_detect, "
107 "failed to reach stable state %x != %x\n", val, val2);
110 static int msm_gpio_clear_detect_status(struct msm_gpio_chip *msm_chip,
113 unsigned bit = BIT(offset);
115 #if MSM_GPIO_BROKEN_INT_CLEAR
116 /* Save interrupts that already triggered before we loose them. */
117 /* Any interrupt that triggers between the read of int_status */
118 /* and the write to int_clear will still be lost though. */
119 msm_chip->int_status_copy |= readl(msm_chip->regs.int_status);
120 msm_chip->int_status_copy &= ~bit;
122 writel(bit, msm_chip->regs.int_clear);
123 msm_gpio_update_both_edge_detect(msm_chip);
127 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
129 struct msm_gpio_chip *msm_chip;
130 unsigned long irq_flags;
132 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
133 spin_lock_irqsave(&msm_chip->lock, irq_flags);
134 writel(readl(msm_chip->regs.oe) & ~BIT(offset), msm_chip->regs.oe);
135 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
140 msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
142 struct msm_gpio_chip *msm_chip;
143 unsigned long irq_flags;
145 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
146 spin_lock_irqsave(&msm_chip->lock, irq_flags);
147 msm_gpio_write(msm_chip, offset, value);
148 writel(readl(msm_chip->regs.oe) | BIT(offset), msm_chip->regs.oe);
149 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
153 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
155 struct msm_gpio_chip *msm_chip;
157 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
158 return (readl(msm_chip->regs.in) & (1U << offset)) ? 1 : 0;
161 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
163 struct msm_gpio_chip *msm_chip;
164 unsigned long irq_flags;
166 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
167 spin_lock_irqsave(&msm_chip->lock, irq_flags);
168 msm_gpio_write(msm_chip, offset, value);
169 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
172 static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
174 return MSM_GPIO_TO_INT(chip->base + offset);
177 #ifdef CONFIG_MSM_GPIOMUX
178 static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
180 return msm_gpiomux_get(chip->base + offset);
183 static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
185 msm_gpiomux_put(chip->base + offset);
188 #define msm_gpio_request NULL
189 #define msm_gpio_free NULL
192 struct msm_gpio_chip msm_gpio_chips[] = {
193 #if defined(CONFIG_ARCH_MSM7X00A)
194 MSM_GPIO_BANK(0, 0, 15),
195 MSM_GPIO_BANK(1, 16, 42),
196 MSM_GPIO_BANK(2, 43, 67),
197 MSM_GPIO_BANK(3, 68, 94),
198 MSM_GPIO_BANK(4, 95, 106),
199 MSM_GPIO_BANK(5, 107, 121),
200 #elif defined(CONFIG_ARCH_MSM7X30)
201 MSM_GPIO_BANK(0, 0, 15),
202 MSM_GPIO_BANK(1, 16, 43),
203 MSM_GPIO_BANK(2, 44, 67),
204 MSM_GPIO_BANK(3, 68, 94),
205 MSM_GPIO_BANK(4, 95, 106),
206 MSM_GPIO_BANK(5, 107, 133),
207 MSM_GPIO_BANK(6, 134, 150),
208 MSM_GPIO_BANK(7, 151, 181),
209 #elif defined(CONFIG_ARCH_QSD8X50)
210 MSM_GPIO_BANK(0, 0, 15),
211 MSM_GPIO_BANK(1, 16, 42),
212 MSM_GPIO_BANK(2, 43, 67),
213 MSM_GPIO_BANK(3, 68, 94),
214 MSM_GPIO_BANK(4, 95, 103),
215 MSM_GPIO_BANK(5, 104, 121),
216 MSM_GPIO_BANK(6, 122, 152),
217 MSM_GPIO_BANK(7, 153, 164),
221 static void msm_gpio_irq_ack(struct irq_data *d)
223 unsigned long irq_flags;
224 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
225 spin_lock_irqsave(&msm_chip->lock, irq_flags);
226 msm_gpio_clear_detect_status(msm_chip,
227 d->irq - gpio_to_irq(msm_chip->chip.base));
228 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
231 static void msm_gpio_irq_mask(struct irq_data *d)
233 unsigned long irq_flags;
234 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
235 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
237 spin_lock_irqsave(&msm_chip->lock, irq_flags);
238 /* level triggered interrupts are also latched */
239 if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
240 msm_gpio_clear_detect_status(msm_chip, offset);
241 msm_chip->int_enable[0] &= ~BIT(offset);
242 writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
243 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
246 static void msm_gpio_irq_unmask(struct irq_data *d)
248 unsigned long irq_flags;
249 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
250 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
252 spin_lock_irqsave(&msm_chip->lock, irq_flags);
253 /* level triggered interrupts are also latched */
254 if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
255 msm_gpio_clear_detect_status(msm_chip, offset);
256 msm_chip->int_enable[0] |= BIT(offset);
257 writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
258 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
261 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
263 unsigned long irq_flags;
264 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
265 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
267 spin_lock_irqsave(&msm_chip->lock, irq_flags);
270 msm_chip->int_enable[1] |= BIT(offset);
272 msm_chip->int_enable[1] &= ~BIT(offset);
274 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
278 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
280 unsigned long irq_flags;
281 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
282 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
283 unsigned val, mask = BIT(offset);
285 spin_lock_irqsave(&msm_chip->lock, irq_flags);
286 val = readl(msm_chip->regs.int_edge);
287 if (flow_type & IRQ_TYPE_EDGE_BOTH) {
288 writel(val | mask, msm_chip->regs.int_edge);
289 __irq_set_handler_locked(d->irq, handle_edge_irq);
291 writel(val & ~mask, msm_chip->regs.int_edge);
292 __irq_set_handler_locked(d->irq, handle_level_irq);
294 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
295 msm_chip->both_edge_detect |= mask;
296 msm_gpio_update_both_edge_detect(msm_chip);
298 msm_chip->both_edge_detect &= ~mask;
299 val = readl(msm_chip->regs.int_pos);
300 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
301 writel(val | mask, msm_chip->regs.int_pos);
303 writel(val & ~mask, msm_chip->regs.int_pos);
305 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
309 static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
314 for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
315 struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i];
316 val = readl(msm_chip->regs.int_status);
317 val &= msm_chip->int_enable[0];
321 /* printk("%s %08x %08x bit %d gpio %d irq %d\n",
322 __func__, v, m, j, msm_chip->chip.start + j,
323 FIRST_GPIO_IRQ + msm_chip->chip.start + j); */
325 generic_handle_irq(FIRST_GPIO_IRQ +
326 msm_chip->chip.base + j);
329 desc->irq_data.chip->irq_ack(&desc->irq_data);
332 static struct irq_chip msm_gpio_irq_chip = {
334 .irq_ack = msm_gpio_irq_ack,
335 .irq_mask = msm_gpio_irq_mask,
336 .irq_unmask = msm_gpio_irq_unmask,
337 .irq_set_wake = msm_gpio_irq_set_wake,
338 .irq_set_type = msm_gpio_irq_set_type,
341 static int __init msm_init_gpio(void)
345 for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) {
346 if (i - FIRST_GPIO_IRQ >=
347 msm_gpio_chips[j].chip.base +
348 msm_gpio_chips[j].chip.ngpio)
350 irq_set_chip_data(i, &msm_gpio_chips[j]);
351 irq_set_chip_and_handler(i, &msm_gpio_irq_chip,
353 set_irq_flags(i, IRQF_VALID);
356 for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
357 spin_lock_init(&msm_gpio_chips[i].lock);
358 writel(0, msm_gpio_chips[i].regs.int_en);
359 gpiochip_add(&msm_gpio_chips[i].chip);
362 irq_set_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
363 irq_set_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
364 irq_set_irq_wake(INT_GPIO_GROUP1, 1);
365 irq_set_irq_wake(INT_GPIO_GROUP2, 2);
369 postcore_initcall(msm_init_gpio);