arch/arm/mach-msm/devices-qsd8x50.c

   1 /*
   2  * Copyright (C) 2008 Google, Inc.
   3  * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/platform_device.h>
  18
  19 #include <linux/dma-mapping.h>
  20 #include <mach/irqs.h>
  21 #include <mach/msm_iomap.h>
  22 #include <mach/dma.h>
  23 #include <mach/board.h>
  24
  25 #include "devices.h"
  26
  27 #include <asm/mach/flash.h>
  28
  29 #include <mach/mmc.h>
  30 #include "clock-pcom.h"
  31
  32 static struct resource resources_uart3[] = {
  33         {
  34                 .start  = INT_UART3,
  35                 .end    = INT_UART3,
  36                 .flags  = IORESOURCE_IRQ,
  37         },
  38         {
  39                 .start  = MSM_UART3_PHYS,
  40                 .end    = MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
  41                 .flags  = IORESOURCE_MEM,
  42                 .name  = "uart_resource"
  43         },
  44 };
  45
  46 struct platform_device msm_device_uart3 = {
  47         .name   = "msm_serial",
  48         .id     = 2,
  49         .num_resources  = ARRAY_SIZE(resources_uart3),
  50         .resource       = resources_uart3,
  51 };
  52
  53 struct platform_device msm_device_smd = {
  54         .name   = "msm_smd",
  55         .id     = -1,
  56 };
  57
  58 static struct resource resources_otg[] = {
  59         {
  60                 .start  = MSM_HSUSB_PHYS,
  61                 .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
  62                 .flags  = IORESOURCE_MEM,
  63         },
  64         {
  65                 .start  = INT_USB_HS,
  66                 .end    = INT_USB_HS,
  67                 .flags  = IORESOURCE_IRQ,
  68         },
  69 };
  70
  71 struct platform_device msm_device_otg = {
  72         .name           = "msm_otg",
  73         .id             = -1,
  74         .num_resources  = ARRAY_SIZE(resources_otg),
  75         .resource       = resources_otg,
  76         .dev            = {
  77                 .coherent_dma_mask      = 0xffffffff,
  78         },
  79 };
  80
  81 static struct resource resources_hsusb[] = {
  82         {
  83                 .start  = MSM_HSUSB_PHYS,
  84                 .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
  85                 .flags  = IORESOURCE_MEM,
  86         },
  87         {
  88                 .start  = INT_USB_HS,
  89                 .end    = INT_USB_HS,
  90                 .flags  = IORESOURCE_IRQ,
  91         },
  92 };
  93
  94 struct platform_device msm_device_hsusb = {
  95         .name           = "msm_hsusb",
  96         .id             = -1,
  97         .num_resources  = ARRAY_SIZE(resources_hsusb),
  98         .resource       = resources_hsusb,
  99         .dev            = {
 100                 .coherent_dma_mask      = 0xffffffff,
 101         },
 102 };
 103
 104 static u64 dma_mask = 0xffffffffULL;
 105 static struct resource resources_hsusb_host[] = {
 106         {
 107                 .start  = MSM_HSUSB_PHYS,
 108                 .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
 109                 .flags  = IORESOURCE_MEM,
 110         },
 111         {
 112                 .start  = INT_USB_HS,
 113                 .end    = INT_USB_HS,
 114                 .flags  = IORESOURCE_IRQ,
 115         },
 116 };
 117
 118 struct platform_device msm_device_hsusb_host = {
 119         .name           = "msm_hsusb_host",
 120         .id             = -1,
 121         .num_resources  = ARRAY_SIZE(resources_hsusb_host),
 122         .resource       = resources_hsusb_host,
 123         .dev            = {
 124                 .dma_mask               = &dma_mask,
 125                 .coherent_dma_mask      = 0xffffffffULL,
 126         },
 127 };
 128
 129 static struct resource resources_sdc1[] = {
 130         {
 131                 .start  = MSM_SDC1_PHYS,
 132                 .end    = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1,
 133                 .flags  = IORESOURCE_MEM,
 134         },
 135         {
 136                 .start  = INT_SDC1_0,
 137                 .end    = INT_SDC1_0,
 138                 .flags  = IORESOURCE_IRQ,
 139                 .name   = "cmd_irq",
 140         },
 141         {
 142                 .start  = INT_SDC1_1,
 143                 .end    = INT_SDC1_1,
 144                 .flags  = IORESOURCE_IRQ,
 145                 .name   = "pio_irq",
 146         },
 147         {
 148                 .flags  = IORESOURCE_IRQ | IORESOURCE_DISABLED,
 149                 .name   = "status_irq"
 150         },
 151         {
 152                 .start  = 8,
 153                 .end    = 8,
 154                 .flags  = IORESOURCE_DMA,
 155         },
 156 };
 157
 158 static struct resource resources_sdc2[] = {
 159         {
 160                 .start  = MSM_SDC2_PHYS,
 161                 .end    = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1,
 162                 .flags  = IORESOURCE_MEM,
 163         },
 164         {
 165                 .start  = INT_SDC2_0,
 166                 .end    = INT_SDC2_0,
 167                 .flags  = IORESOURCE_IRQ,
 168                 .name   = "cmd_irq",
 169         },
 170                 {
 171                 .start  = INT_SDC2_1,
 172                 .end    = INT_SDC2_1,
 173                 .flags  = IORESOURCE_IRQ,
 174                 .name   = "pio_irq",
 175         },
 176         {
 177                 .flags  = IORESOURCE_IRQ | IORESOURCE_DISABLED,
 178                 .name   = "status_irq"
 179         },
 180         {
 181                 .start  = 8,
 182                 .end    = 8,
 183                 .flags  = IORESOURCE_DMA,
 184         },
 185 };
 186
 187 static struct resource resources_sdc3[] = {
 188         {
 189                 .start  = MSM_SDC3_PHYS,
 190                 .end    = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1,
 191                 .flags  = IORESOURCE_MEM,
 192         },
 193         {
 194                 .start  = INT_SDC3_0,
 195                 .end    = INT_SDC3_0,
 196                 .flags  = IORESOURCE_IRQ,
 197                 .name   = "cmd_irq",
 198         },
 199                 {
 200                 .start  = INT_SDC3_1,
 201                 .end    = INT_SDC3_1,
 202                 .flags  = IORESOURCE_IRQ,
 203                 .name   = "pio_irq",
 204         },
 205         {
 206                 .flags  = IORESOURCE_IRQ | IORESOURCE_DISABLED,
 207                 .name   = "status_irq"
 208         },
 209         {
 210                 .start  = 8,
 211                 .end    = 8,
 212                 .flags  = IORESOURCE_DMA,
 213         },
 214 };
 215
 216 static struct resource resources_sdc4[] = {
 217         {
 218                 .start  = MSM_SDC4_PHYS,
 219                 .end    = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1,
 220                 .flags  = IORESOURCE_MEM,
 221         },
 222         {
 223                 .start  = INT_SDC4_0,
 224                 .end    = INT_SDC4_0,
 225                 .flags  = IORESOURCE_IRQ,
 226                 .name   = "cmd_irq",
 227         },
 228                 {
 229                 .start  = INT_SDC4_1,
 230                 .end    = INT_SDC4_1,
 231                 .flags  = IORESOURCE_IRQ,
 232                 .name   = "pio_irq",
 233         },
 234         {
 235                 .flags  = IORESOURCE_IRQ | IORESOURCE_DISABLED,
 236                 .name   = "status_irq"
 237         },
 238         {
 239                 .start  = 8,
 240                 .end    = 8,
 241                 .flags  = IORESOURCE_DMA,
 242         },
 243 };
 244
 245 struct platform_device msm_device_sdc1 = {
 246         .name           = "msm_sdcc",
 247         .id             = 1,
 248         .num_resources  = ARRAY_SIZE(resources_sdc1),
 249         .resource       = resources_sdc1,
 250         .dev            = {
 251                 .coherent_dma_mask      = 0xffffffff,
 252         },
 253 };
 254
 255 struct platform_device msm_device_sdc2 = {
 256         .name           = "msm_sdcc",
 257         .id             = 2,
 258         .num_resources  = ARRAY_SIZE(resources_sdc2),
 259         .resource       = resources_sdc2,
 260         .dev            = {
 261                 .coherent_dma_mask      = 0xffffffff,
 262         },
 263 };
 264
 265 struct platform_device msm_device_sdc3 = {
 266         .name           = "msm_sdcc",
 267         .id             = 3,
 268         .num_resources  = ARRAY_SIZE(resources_sdc3),
 269         .resource       = resources_sdc3,
 270         .dev            = {
 271                 .coherent_dma_mask      = 0xffffffff,
 272         },
 273 };
 274
 275 struct platform_device msm_device_sdc4 = {
 276         .name           = "msm_sdcc",
 277         .id             = 4,
 278         .num_resources  = ARRAY_SIZE(resources_sdc4),
 279         .resource       = resources_sdc4,
 280         .dev            = {
 281                 .coherent_dma_mask      = 0xffffffff,
 282         },
 283 };
 284
 285 static struct platform_device *msm_sdcc_devices[] __initdata = {
 286         &msm_device_sdc1,
 287         &msm_device_sdc2,
 288         &msm_device_sdc3,
 289         &msm_device_sdc4,
 290 };
 291
 292 int __init msm_add_sdcc(unsigned int controller,
 293                         struct msm_mmc_platform_data *plat,
 294                         unsigned int stat_irq, unsigned long stat_irq_flags)
 295 {
 296         struct platform_device  *pdev;
 297         struct resource *res;
 298
 299         if (controller < 1 || controller > 4)
 300                 return -EINVAL;
 301
 302         pdev = msm_sdcc_devices[controller-1];
 303         pdev->dev.platform_data = plat;
 304
 305         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq");
 306         if (!res)
 307                 return -EINVAL;
 308         else if (stat_irq) {
 309                 res->start = res->end = stat_irq;
 310                 res->flags &= ~IORESOURCE_DISABLED;
 311                 res->flags |= stat_irq_flags;
 312         }
 313
 314         return platform_device_register(pdev);
 315 }
 316
 317 struct clk msm_clocks_8x50[] = {
 318         CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
 319         CLK_PCOM("ce_clk",      CE_CLK,         NULL, 0),
 320         CLK_PCOM("ebi1_clk",    EBI1_CLK,       NULL, CLK_MIN),
 321         CLK_PCOM("ebi2_clk",    EBI2_CLK,       NULL, 0),
 322         CLK_PCOM("ecodec_clk",  ECODEC_CLK,     NULL, 0),
 323         CLK_PCOM("emdh_clk",    EMDH_CLK,       NULL, OFF | CLK_MINMAX),
 324         CLK_PCOM("gp_clk",      GP_CLK,         NULL, 0),
 325         CLK_PCOM("grp_clk",     GRP_3D_CLK,     NULL, 0),
 326         CLK_PCOM("i2c_clk",     I2C_CLK,        NULL, 0),
 327         CLK_PCOM("icodec_rx_clk",       ICODEC_RX_CLK,  NULL, 0),
 328         CLK_PCOM("icodec_tx_clk",       ICODEC_TX_CLK,  NULL, 0),
 329         CLK_PCOM("imem_clk",    IMEM_CLK,       NULL, OFF),
 330         CLK_PCOM("mdc_clk",     MDC_CLK,        NULL, 0),
 331         CLK_PCOM("mddi_clk",    PMDH_CLK,       NULL, OFF | CLK_MINMAX),
 332         CLK_PCOM("mdp_clk",     MDP_CLK,        NULL, OFF),
 333         CLK_PCOM("mdp_lcdc_pclk_clk", MDP_LCDC_PCLK_CLK, NULL, 0),
 334         CLK_PCOM("mdp_lcdc_pad_pclk_clk", MDP_LCDC_PAD_PCLK_CLK, NULL, 0),
 335         CLK_PCOM("mdp_vsync_clk",       MDP_VSYNC_CLK,  NULL, 0),
 336         CLK_PCOM("pbus_clk",    PBUS_CLK,       NULL, CLK_MIN),
 337         CLK_PCOM("pcm_clk",     PCM_CLK,        NULL, 0),
 338         CLK_PCOM("sdac_clk",    SDAC_CLK,       NULL, OFF),
 339         CLK_PCOM("sdc_clk",     SDC1_CLK,       &msm_device_sdc1.dev, OFF),
 340         CLK_PCOM("sdc_pclk",    SDC1_P_CLK,     &msm_device_sdc1.dev, OFF),
 341         CLK_PCOM("sdc_clk",     SDC2_CLK,       &msm_device_sdc2.dev, OFF),
 342         CLK_PCOM("sdc_pclk",    SDC2_P_CLK,     &msm_device_sdc2.dev, OFF),
 343         CLK_PCOM("sdc_clk",     SDC3_CLK,       &msm_device_sdc3.dev, OFF),
 344         CLK_PCOM("sdc_pclk",    SDC3_P_CLK,     &msm_device_sdc3.dev, OFF),
 345         CLK_PCOM("sdc_clk",     SDC4_CLK,       &msm_device_sdc4.dev, OFF),
 346         CLK_PCOM("sdc_pclk",    SDC4_P_CLK,     &msm_device_sdc4.dev, OFF),
 347         CLK_PCOM("spi_clk",     SPI_CLK,        NULL, 0),
 348         CLK_PCOM("tsif_clk",    TSIF_CLK,       NULL, 0),
 349         CLK_PCOM("tsif_ref_clk",        TSIF_REF_CLK,   NULL, 0),
 350         CLK_PCOM("tv_dac_clk",  TV_DAC_CLK,     NULL, 0),
 351         CLK_PCOM("tv_enc_clk",  TV_ENC_CLK,     NULL, 0),
 352         CLK_PCOM("uart_clk",    UART1_CLK,      NULL, OFF),
 353         CLK_PCOM("uart_clk",    UART2_CLK,      NULL, 0),
 354         CLK_PCOM("uart_clk",    UART3_CLK,      &msm_device_uart3.dev, OFF),
 355         CLK_PCOM("uartdm_clk",  UART1DM_CLK,    NULL, OFF),
 356         CLK_PCOM("uartdm_clk",  UART2DM_CLK,    NULL, 0),
 357         CLK_PCOM("usb_hs_clk",  USB_HS_CLK,     NULL, OFF),
 358         CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK,   NULL, OFF),
 359         CLK_PCOM("usb_otg_clk", USB_OTG_CLK,    NULL, 0),
 360         CLK_PCOM("vdc_clk",     VDC_CLK,        NULL, OFF | CLK_MIN),
 361         CLK_PCOM("vfe_clk",     VFE_CLK,        NULL, OFF),
 362         CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK,    NULL, OFF),
 363         CLK_PCOM("vfe_axi_clk", VFE_AXI_CLK,    NULL, OFF),
 364         CLK_PCOM("usb_hs2_clk", USB_HS2_CLK,    NULL, OFF),
 365         CLK_PCOM("usb_hs2_pclk",        USB_HS2_P_CLK,  NULL, OFF),
 366         CLK_PCOM("usb_hs3_clk", USB_HS3_CLK,    NULL, OFF),
 367         CLK_PCOM("usb_hs3_pclk",        USB_HS3_P_CLK,  NULL, OFF),
 368         CLK_PCOM("usb_phy_clk", USB_PHY_CLK,    NULL, 0),
 369 };
 370
 371 unsigned msm_num_clocks_8x50 = ARRAY_SIZE(msm_clocks_8x50);
 372