1 // SPDX-License-Identifier: GPL-2.0
3 * Configuration for MediaTek MT8512 SoC
5 * Copyright (C) 2019 MediaTek Inc.
6 * Author: Mingming Lee <mingming.lee@mediatek.com>
16 #include <asm/arch/misc.h>
17 #include <asm/armv8/mmu.h>
18 #include <asm/cache.h>
19 #include <asm/sections.h>
20 #include <dm/uclass.h>
21 #include <dt-bindings/clock/mt8512-clk.h>
23 DECLARE_GLOBAL_DATA_PTR;
27 return fdtdec_setup_mem_size_base();
30 phys_size_t get_effective_memsize(void)
32 /* limit stack below tee reserve memory */
33 return gd->ram_size - 6 * SZ_1M;
36 int dram_init_banksize(void)
38 gd->bd->bi_dram[0].start = gd->ram_base;
39 gd->bd->bi_dram[0].size = get_effective_memsize();
44 void reset_cpu(ulong addr)
46 struct udevice *watchdog_dev = NULL;
48 if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev))
49 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev))
52 wdt_expire_now(watchdog_dev, 0);
55 int print_cpuinfo(void)
57 debug("CPU: MediaTek MT8512\n");
61 static struct mm_region mt8512_mem_map[] = {
67 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
72 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
74 PTE_BLOCK_PXN | PTE_BLOCK_UXN
80 struct mm_region *mem_map = mt8512_mem_map;