2 * arch/arm/mach-lpc32xx/common.c
4 * Author: Kevin Wells <kevin.wells@nxp.com>
6 * Copyright (C) 2010 NXP Semiconductors
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/err.h>
24 #include <linux/i2c.h>
25 #include <linux/i2c-pnx.h>
28 #include <asm/mach/map.h>
31 #include <mach/hardware.h>
32 #include <mach/platform.h>
38 static struct resource watchdog_resources[] = {
40 .start = LPC32XX_WDTIM_BASE,
41 .end = LPC32XX_WDTIM_BASE + SZ_4K - 1,
42 .flags = IORESOURCE_MEM,
46 struct platform_device lpc32xx_watchdog_device = {
47 .name = "pnx4008-watchdog",
49 .num_resources = ARRAY_SIZE(watchdog_resources),
50 .resource = watchdog_resources,
56 static struct i2c_pnx_data i2c0_data = {
57 .name = I2C_CHIP_NAME "1",
58 .base = LPC32XX_I2C1_BASE,
59 .irq = IRQ_LPC32XX_I2C_1,
62 static struct i2c_pnx_data i2c1_data = {
63 .name = I2C_CHIP_NAME "2",
64 .base = LPC32XX_I2C2_BASE,
65 .irq = IRQ_LPC32XX_I2C_2,
68 static struct i2c_pnx_data i2c2_data = {
70 .base = LPC32XX_OTG_I2C_BASE,
71 .irq = IRQ_LPC32XX_USB_I2C,
74 struct platform_device lpc32xx_i2c0_device = {
78 .platform_data = &i2c0_data,
82 struct platform_device lpc32xx_i2c1_device = {
86 .platform_data = &i2c1_data,
90 struct platform_device lpc32xx_i2c2_device = {
94 .platform_data = &i2c2_data,
99 * Returns the unique ID for the device
101 void lpc32xx_get_uid(u32 devid[4])
105 for (i = 0; i < 4; i++)
106 devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2));
110 * Returns SYSCLK source
111 * 0 = PLL397, 1 = main oscillator
113 int clk_is_sysclk_mainosc(void)
115 if ((__raw_readl(LPC32XX_CLKPWR_SYSCLK_CTRL) &
116 LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX) == 0)
123 * System reset via the watchdog timer
125 void lpc32xx_watchdog_reset(void)
127 /* Make sure WDT clocks are enabled */
128 __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
129 LPC32XX_CLKPWR_TIMER_CLK_CTRL);
131 /* Instant assert of RESETOUT_N with pulse length 1mS */
132 __raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
133 __raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
137 * Detects and returns IRAM size for the device variation
139 #define LPC32XX_IRAM_BANK_SIZE SZ_128K
140 static u32 iram_size;
141 u32 lpc32xx_return_iram_size(void)
143 if (iram_size == 0) {
144 u32 savedval1, savedval2;
145 void __iomem *iramptr1, *iramptr2;
147 iramptr1 = io_p2v(LPC32XX_IRAM_BASE);
148 iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE);
149 savedval1 = __raw_readl(iramptr1);
150 savedval2 = __raw_readl(iramptr2);
152 if (savedval1 == savedval2) {
153 __raw_writel(savedval2 + 1, iramptr2);
154 if (__raw_readl(iramptr1) == savedval2 + 1)
155 iram_size = LPC32XX_IRAM_BANK_SIZE;
157 iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
158 __raw_writel(savedval2, iramptr2);
160 iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
167 * Computes PLL rate from PLL register and input clock
169 u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup)
171 u32 ilfreq, p, m, n, fcco, fref, cfreq;
176 * ifreq must be >= 1MHz and <= 20MHz
177 * FCCO must be >= 156MHz and <= 320MHz
178 * FREF must be >= 1MHz and <= 27MHz
179 * Assume the passed input data is not valid
187 mode = (pllsetup->cco_bypass_b15 << 2) |
188 (pllsetup->direct_output_b14 << 1) |
189 pllsetup->fdbk_div_ctrl_b13;
192 case 0x0: /* Non-integer mode */
193 cfreq = (m * ilfreq) / (2 * p * n);
194 fcco = (m * ilfreq) / n;
198 case 0x1: /* integer mode */
199 cfreq = (m * ilfreq) / n;
200 fcco = (m * ilfreq) / (n * 2 * p);
205 case 0x3: /* Direct mode */
206 cfreq = (m * ilfreq) / n;
212 case 0x5: /* Bypass mode */
213 cfreq = ilfreq / (2 * p);
219 case 0x7: /* Direct bypass mode */
227 if (fcco < 156000000 || fcco > 320000000)
230 if (fref < 1000000 || fref > 27000000)
236 u32 clk_get_pclk_div(void)
238 return 1 + ((__raw_readl(LPC32XX_CLKPWR_HCLK_DIV) >> 2) & 0x1F);
241 static struct map_desc lpc32xx_io_desc[] __initdata = {
243 .virtual = IO_ADDRESS(LPC32XX_AHB0_START),
244 .pfn = __phys_to_pfn(LPC32XX_AHB0_START),
245 .length = LPC32XX_AHB0_SIZE,
249 .virtual = IO_ADDRESS(LPC32XX_AHB1_START),
250 .pfn = __phys_to_pfn(LPC32XX_AHB1_START),
251 .length = LPC32XX_AHB1_SIZE,
255 .virtual = IO_ADDRESS(LPC32XX_FABAPB_START),
256 .pfn = __phys_to_pfn(LPC32XX_FABAPB_START),
257 .length = LPC32XX_FABAPB_SIZE,
261 .virtual = IO_ADDRESS(LPC32XX_IRAM_BASE),
262 .pfn = __phys_to_pfn(LPC32XX_IRAM_BASE),
263 .length = (LPC32XX_IRAM_BANK_SIZE * 2),
268 void __init lpc32xx_map_io(void)
270 iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));