arch/arm/mach-lpc32xx/clock.c

   1 /*
   2  * arch/arm/mach-lpc32xx/clock.c
   3  *
   4  * Author: Kevin Wells <kevin.wells@nxp.com>
   5  *
   6  * Copyright (C) 2010 NXP Semiconductors
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 /*
  20  * LPC32xx clock management driver overview
  21  *
  22  * The LPC32XX contains a number of high level system clocks that can be
  23  * generated from different sources. These system clocks are used to
  24  * generate the CPU and bus rates and the individual peripheral clocks in
  25  * the system. When Linux is started by the boot loader, the system
  26  * clocks are already running. Stopping a system clock during normal
  27  * Linux operation should never be attempted, as peripherals that require
  28  * those clocks will quit working (ie, DRAM).
  29  *
  30  * The LPC32xx high level clock tree looks as follows. Clocks marked with
  31  * an asterisk are always on and cannot be disabled. Clocks marked with
  32  * an ampersand can only be disabled in CPU suspend mode. Clocks marked
  33  * with a caret are always on if it is the selected clock for the SYSCLK
  34  * source. The clock that isn't used for SYSCLK can be enabled and
  35  * disabled normally.
  36  *                               32KHz oscillator*
  37  *                               /      |      \
  38  *                             RTC*   PLL397^ TOUCH
  39  *                                     /
  40  *               Main oscillator^     /
  41  *                   |        \      /
  42  *                   |         SYSCLK&
  43  *                   |            \
  44  *                   |             \
  45  *                USB_PLL       HCLK_PLL&
  46  *                   |           |    |
  47  *            USB host/device  PCLK&  |
  48  *                               |    |
  49  *                             Peripherals
  50  *
  51  * The CPU and chip bus rates are derived from the HCLK PLL, which can
  52  * generate various clock rates up to 266MHz and beyond. The internal bus
  53  * rates (PCLK and HCLK) are generated from dividers based on the HCLK
  54  * PLL rate. HCLK can be a ratio of 1:1, 1:2, or 1:4 or HCLK PLL rate,
  55  * while PCLK can be 1:1 to 1:32 of HCLK PLL rate. Most peripherals high
  56  * level clocks are based on either HCLK or PCLK, but have their own
  57  * dividers as part of the IP itself. Because of this, the system clock
  58  * rates should not be changed.
  59  *
  60  * The HCLK PLL is clocked from SYSCLK, which can be derived from the
  61  * main oscillator or PLL397. PLL397 generates a rate that is 397 times
  62  * the 32KHz oscillator rate. The main oscillator runs at the selected
  63  * oscillator/crystal rate on the mosc_in pin of the LPC32xx. This rate
  64  * is normally 13MHz, but depends on the selection of external crystals
  65  * or oscillators. If USB operation is required, the main oscillator must
  66  * be used in the system.
  67  *
  68  * Switching SYSCLK between sources during normal Linux operation is not
  69  * supported. SYSCLK is preset in the bootloader. Because of the
  70  * complexities of clock management during clock frequency changes,
  71  * there are some limitations to the clock driver explained below:
  72  * - The PLL397 and main oscillator can be enabled and disabled by the
  73  *   clk_enable() and clk_disable() functions unless SYSCLK is based
  74  *   on that clock. This allows the other oscillator that isn't driving
  75  *   the HCLK PLL to be used as another system clock that can be routed
  76  *   to an external pin.
  77  * - The muxed SYSCLK input and HCLK_PLL rate cannot be changed with
  78  *   this driver.
  79  * - HCLK and PCLK rates cannot be changed as part of this driver.
  80  * - Most peripherals have their own dividers are part of the peripheral
  81  *   block. Changing SYSCLK, HCLK PLL, HCLK, or PCLK sources or rates
  82  *   will also impact the individual peripheral rates.
  83  */
  84
  85 #include <linux/export.h>
  86 #include <linux/kernel.h>
  87 #include <linux/list.h>
  88 #include <linux/errno.h>
  89 #include <linux/device.h>
  90 #include <linux/delay.h>
  91 #include <linux/err.h>
  92 #include <linux/clk.h>
  93 #include <linux/amba/bus.h>
  94 #include <linux/amba/clcd.h>
  95 #include <linux/clkdev.h>
  96
  97 #include <mach/hardware.h>
  98 #include <mach/platform.h>
  99 #include "clock.h"
 100 #include "common.h"
 101
 102 static DEFINE_SPINLOCK(global_clkregs_lock);
 103
 104 static int usb_pll_enable, usb_pll_valid;
 105
 106 static struct clk clk_armpll;
 107 static struct clk clk_usbpll;
 108
 109 /*
 110  * Post divider values for PLLs based on selected register value
 111  */
 112 static const u32 pll_postdivs[4] = {1, 2, 4, 8};
 113
 114 static unsigned long local_return_parent_rate(struct clk *clk)
 115 {
 116         /*
 117          * If a clock has a rate of 0, then it inherits it's parent
 118          * clock rate
 119          */
 120         while (clk->rate == 0)
 121                 clk = clk->parent;
 122
 123         return clk->rate;
 124 }
 125
 126 /* 32KHz clock has a fixed rate and is not stoppable */
 127 static struct clk osc_32KHz = {
 128         .rate           = LPC32XX_CLOCK_OSC_FREQ,
 129         .get_rate       = local_return_parent_rate,
 130 };
 131
 132 static int local_pll397_enable(struct clk *clk, int enable)
 133 {
 134         u32 reg;
 135         unsigned long timeout = jiffies + msecs_to_jiffies(10);
 136
 137         reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL);
 138
 139         if (enable == 0) {
 140                 reg |= LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
 141                 __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
 142         } else {
 143                 /* Enable PLL397 */
 144                 reg &= ~LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
 145                 __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
 146
 147                 /* Wait for PLL397 lock */
 148                 while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
 149                         LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
 150                         time_before(jiffies, timeout))
 151                         cpu_relax();
 152
 153                 if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
 154                         LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0)
 155                         return -ENODEV;
 156         }
 157
 158         return 0;
 159 }
 160
 161 static int local_oscmain_enable(struct clk *clk, int enable)
 162 {
 163         u32 reg;
 164         unsigned long timeout = jiffies + msecs_to_jiffies(10);
 165
 166         reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL);
 167
 168         if (enable == 0) {
 169                 reg |= LPC32XX_CLKPWR_MOSC_DISABLE;
 170                 __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
 171         } else {
 172                 /* Enable main oscillator */
 173                 reg &= ~LPC32XX_CLKPWR_MOSC_DISABLE;
 174                 __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
 175
 176                 /* Wait for main oscillator to start */
 177                 while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
 178                         LPC32XX_CLKPWR_MOSC_DISABLE) != 0) &&
 179                         time_before(jiffies, timeout))
 180                         cpu_relax();
 181
 182                 if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
 183                         LPC32XX_CLKPWR_MOSC_DISABLE) != 0)
 184                         return -ENODEV;
 185         }
 186
 187         return 0;
 188 }
 189
 190 static struct clk osc_pll397 = {
 191         .parent         = &osc_32KHz,
 192         .enable         = local_pll397_enable,
 193         .rate           = LPC32XX_CLOCK_OSC_FREQ * 397,
 194         .get_rate       = local_return_parent_rate,
 195 };
 196
 197 static struct clk osc_main = {
 198         .enable         = local_oscmain_enable,
 199         .rate           = LPC32XX_MAIN_OSC_FREQ,
 200         .get_rate       = local_return_parent_rate,
 201 };
 202
 203 static struct clk clk_sys;
 204
 205 /*
 206  * Convert a PLL register value to a PLL output frequency
 207  */
 208 u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval)
 209 {
 210         struct clk_pll_setup pllcfg;
 211
 212         pllcfg.cco_bypass_b15 = 0;
 213         pllcfg.direct_output_b14 = 0;
 214         pllcfg.fdbk_div_ctrl_b13 = 0;
 215         if ((regval & LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS) != 0)
 216                 pllcfg.cco_bypass_b15 = 1;
 217         if ((regval & LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS) != 0)
 218                 pllcfg.direct_output_b14 = 1;
 219         if ((regval & LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK) != 0)
 220                 pllcfg.fdbk_div_ctrl_b13 = 1;
 221         pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF);
 222         pllcfg.pll_n = 1 + ((regval >> 9) & 0x3);
 223         pllcfg.pll_p = pll_postdivs[((regval >> 11) & 0x3)];
 224
 225         return clk_check_pll_setup(inputclk, &pllcfg);
 226 }
 227
 228 /*
 229  * Setup the HCLK PLL with a PLL structure
 230  */
 231 static u32 local_clk_pll_setup(struct clk_pll_setup *PllSetup)
 232 {
 233         u32 tv, tmp = 0;
 234
 235         if (PllSetup->analog_on != 0)
 236                 tmp |= LPC32XX_CLKPWR_HCLKPLL_POWER_UP;
 237         if (PllSetup->cco_bypass_b15 != 0)
 238                 tmp |= LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS;
 239         if (PllSetup->direct_output_b14 != 0)
 240                 tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS;
 241         if (PllSetup->fdbk_div_ctrl_b13 != 0)
 242                 tmp |= LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK;
 243
 244         tv = ffs(PllSetup->pll_p) - 1;
 245         if ((!is_power_of_2(PllSetup->pll_p)) || (tv > 3))
 246                 return 0;
 247
 248         tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(tv);
 249         tmp |= LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(PllSetup->pll_n - 1);
 250         tmp |= LPC32XX_CLKPWR_HCLKPLL_PLLM(PllSetup->pll_m - 1);
 251
 252         return tmp;
 253 }
 254
 255 /*
 256  * Update the ARM core PLL frequency rate variable from the actual PLL setting
 257  */
 258 static void local_update_armpll_rate(void)
 259 {
 260         u32 clkin, pllreg;
 261
 262         clkin = clk_armpll.parent->rate;
 263         pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
 264
 265         clk_armpll.rate = clk_get_pllrate_from_reg(clkin, pllreg);
 266 }
 267
 268 /*
 269  * Find a PLL configuration for the selected input frequency
 270  */
 271 static u32 local_clk_find_pll_cfg(u32 pllin_freq, u32 target_freq,
 272         struct clk_pll_setup *pllsetup)
 273 {
 274         u32 ifreq, freqtol, m, n, p, fclkout;
 275
 276         /* Determine frequency tolerance limits */
 277         freqtol = target_freq / 250;
 278         ifreq = pllin_freq;
 279
 280         /* Is direct bypass mode possible? */
 281         if (abs(pllin_freq - target_freq) <= freqtol) {
 282                 pllsetup->analog_on = 0;
 283                 pllsetup->cco_bypass_b15 = 1;
 284                 pllsetup->direct_output_b14 = 1;
 285                 pllsetup->fdbk_div_ctrl_b13 = 1;
 286                 pllsetup->pll_p = pll_postdivs[0];
 287                 pllsetup->pll_n = 1;
 288                 pllsetup->pll_m = 1;
 289                 return clk_check_pll_setup(ifreq, pllsetup);
 290         } else if (target_freq <= ifreq) {
 291                 pllsetup->analog_on = 0;
 292                 pllsetup->cco_bypass_b15 = 1;
 293                 pllsetup->direct_output_b14 = 0;
 294                 pllsetup->fdbk_div_ctrl_b13 = 1;
 295                 pllsetup->pll_n = 1;
 296                 pllsetup->pll_m = 1;
 297                 for (p = 0; p <= 3; p++) {
 298                         pllsetup->pll_p = pll_postdivs[p];
 299                         fclkout = clk_check_pll_setup(ifreq, pllsetup);
 300                         if (abs(target_freq - fclkout) <= freqtol)
 301                                 return fclkout;
 302                 }
 303         }
 304
 305         /* Is direct mode possible? */
 306         pllsetup->analog_on = 1;
 307         pllsetup->cco_bypass_b15 = 0;
 308         pllsetup->direct_output_b14 = 1;
 309         pllsetup->fdbk_div_ctrl_b13 = 0;
 310         pllsetup->pll_p = pll_postdivs[0];
 311         for (m = 1; m <= 256; m++) {
 312                 for (n = 1; n <= 4; n++) {
 313                         /* Compute output frequency for this value */
 314                         pllsetup->pll_n = n;
 315                         pllsetup->pll_m = m;
 316                         fclkout = clk_check_pll_setup(ifreq,
 317                                 pllsetup);
 318                         if (abs(target_freq - fclkout) <=
 319                                 freqtol)
 320                                 return fclkout;
 321                 }
 322         }
 323
 324         /* Is integer mode possible? */
 325         pllsetup->analog_on = 1;
 326         pllsetup->cco_bypass_b15 = 0;
 327         pllsetup->direct_output_b14 = 0;
 328         pllsetup->fdbk_div_ctrl_b13 = 1;
 329         for (m = 1; m <= 256; m++) {
 330                 for (n = 1; n <= 4; n++) {
 331                         for (p = 0; p < 4; p++) {
 332                                 /* Compute output frequency */
 333                                 pllsetup->pll_p = pll_postdivs[p];
 334                                 pllsetup->pll_n = n;
 335                                 pllsetup->pll_m = m;
 336                                 fclkout = clk_check_pll_setup(
 337                                         ifreq, pllsetup);
 338                                 if (abs(target_freq - fclkout) <= freqtol)
 339                                         return fclkout;
 340                         }
 341                 }
 342         }
 343
 344         /* Try non-integer mode */
 345         pllsetup->analog_on = 1;
 346         pllsetup->cco_bypass_b15 = 0;
 347         pllsetup->direct_output_b14 = 0;
 348         pllsetup->fdbk_div_ctrl_b13 = 0;
 349         for (m = 1; m <= 256; m++) {
 350                 for (n = 1; n <= 4; n++) {
 351                         for (p = 0; p < 4; p++) {
 352                                 /* Compute output frequency */
 353                                 pllsetup->pll_p = pll_postdivs[p];
 354                                 pllsetup->pll_n = n;
 355                                 pllsetup->pll_m = m;
 356                                 fclkout = clk_check_pll_setup(
 357                                         ifreq, pllsetup);
 358                                 if (abs(target_freq - fclkout) <= freqtol)
 359                                         return fclkout;
 360                         }
 361                 }
 362         }
 363
 364         return 0;
 365 }
 366
 367 static struct clk clk_armpll = {
 368         .parent         = &clk_sys,
 369         .get_rate       = local_return_parent_rate,
 370 };
 371
 372 /*
 373  * Setup the USB PLL with a PLL structure
 374  */
 375 static u32 local_clk_usbpll_setup(struct clk_pll_setup *pHCLKPllSetup)
 376 {
 377         u32 reg, tmp = local_clk_pll_setup(pHCLKPllSetup);
 378
 379         reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL) & ~0x1FFFF;
 380         reg |= tmp;
 381         __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
 382
 383         return clk_check_pll_setup(clk_usbpll.parent->rate,
 384                 pHCLKPllSetup);
 385 }
 386
 387 static int local_usbpll_enable(struct clk *clk, int enable)
 388 {
 389         u32 reg;
 390         int ret = 0;
 391         unsigned long timeout = jiffies + msecs_to_jiffies(20);
 392
 393         reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
 394
 395         __raw_writel(reg & ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN2 |
 396                 LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP),
 397                 LPC32XX_CLKPWR_USB_CTRL);
 398         __raw_writel(reg & ~LPC32XX_CLKPWR_USBCTRL_CLK_EN1,
 399                 LPC32XX_CLKPWR_USB_CTRL);
 400
 401         if (enable && usb_pll_valid && usb_pll_enable) {
 402                 ret = -ENODEV;
 403                 /*
 404                  * If the PLL rate has been previously set, then the rate
 405                  * in the PLL register is valid and can be enabled here.
 406                  * Otherwise, it needs to be enabled as part of setrate.
 407                  */
 408
 409                 /*
 410                  * Gate clock into PLL
 411                  */
 412                 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
 413                 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
 414
 415                 /*
 416                  * Enable PLL
 417                  */
 418                 reg |= LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP;
 419                 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
 420
 421                 /*
 422                  * Wait for PLL to lock
 423                  */
 424                 while (time_before(jiffies, timeout) && (ret == -ENODEV)) {
 425                         reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
 426                         if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
 427                                 ret = 0;
 428                         else
 429                                 udelay(10);
 430                 }
 431
 432                 /*
 433                  * Gate clock from PLL if PLL is locked
 434                  */
 435                 if (ret == 0) {
 436                         __raw_writel(reg | LPC32XX_CLKPWR_USBCTRL_CLK_EN2,
 437                                 LPC32XX_CLKPWR_USB_CTRL);
 438                 } else {
 439                         __raw_writel(reg & ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
 440                                 LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP),
 441                                 LPC32XX_CLKPWR_USB_CTRL);
 442                 }
 443         } else if ((enable == 0) && usb_pll_valid  && usb_pll_enable) {
 444                 usb_pll_valid = 0;
 445                 usb_pll_enable = 0;
 446         }
 447
 448         return ret;
 449 }
 450
 451 static unsigned long local_usbpll_round_rate(struct clk *clk,
 452         unsigned long rate)
 453 {
 454         u32 clkin, usbdiv;
 455         struct clk_pll_setup pllsetup;
 456
 457         /*
 458          * Unlike other clocks, this clock has a KHz input rate, so bump
 459          * it up to work with the PLL function
 460          */
 461         rate = rate * 1000;
 462
 463         clkin = clk->get_rate(clk);
 464         usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
 465                 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
 466         clkin = clkin / usbdiv;
 467
 468         /* Try to find a good rate setup */
 469         if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
 470                 return 0;
 471
 472         return clk_check_pll_setup(clkin, &pllsetup);
 473 }
 474
 475 static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
 476 {
 477         int ret = -ENODEV;
 478         u32 clkin, usbdiv;
 479         struct clk_pll_setup pllsetup;
 480
 481         /*
 482          * Unlike other clocks, this clock has a KHz input rate, so bump
 483          * it up to work with the PLL function
 484          */
 485         rate = rate * 1000;
 486
 487         clkin = clk->get_rate(clk->parent);
 488         usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
 489                 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
 490         clkin = clkin / usbdiv;
 491
 492         /* Try to find a good rate setup */
 493         if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
 494                 return -EINVAL;
 495
 496         /*
 497          * Disable PLL clocks during PLL change
 498          */
 499         local_usbpll_enable(clk, 0);
 500         pllsetup.analog_on = 0;
 501         local_clk_usbpll_setup(&pllsetup);
 502
 503         /*
 504          * Start USB PLL and check PLL status
 505          */
 506
 507         usb_pll_valid = 1;
 508         usb_pll_enable = 1;
 509
 510         ret = local_usbpll_enable(clk, 1);
 511         if (ret >= 0)
 512                 clk->rate = clk_check_pll_setup(clkin, &pllsetup);
 513
 514         return ret;
 515 }
 516
 517 static struct clk clk_usbpll = {
 518         .parent         = &osc_main,
 519         .set_rate       = local_usbpll_set_rate,
 520         .enable         = local_usbpll_enable,
 521         .rate           = 48000, /* In KHz */
 522         .get_rate       = local_return_parent_rate,
 523         .round_rate     = local_usbpll_round_rate,
 524 };
 525
 526 static u32 clk_get_hclk_div(void)
 527 {
 528         static const u32 hclkdivs[4] = {1, 2, 4, 4};
 529         return hclkdivs[LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(
 530                 __raw_readl(LPC32XX_CLKPWR_HCLK_DIV))];
 531 }
 532
 533 static struct clk clk_hclk = {
 534         .parent         = &clk_armpll,
 535         .get_rate       = local_return_parent_rate,
 536 };
 537
 538 static struct clk clk_pclk = {
 539         .parent         = &clk_armpll,
 540         .get_rate       = local_return_parent_rate,
 541 };
 542
 543 static int local_onoff_enable(struct clk *clk, int enable)
 544 {
 545         u32 tmp;
 546
 547         tmp = __raw_readl(clk->enable_reg);
 548
 549         if (enable == 0)
 550                 tmp &= ~clk->enable_mask;
 551         else
 552                 tmp |= clk->enable_mask;
 553
 554         __raw_writel(tmp, clk->enable_reg);
 555
 556         return 0;
 557 }
 558
 559 /* Peripheral clock sources */
 560 static struct clk clk_timer0 = {
 561         .parent         = &clk_pclk,
 562         .enable         = local_onoff_enable,
 563         .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
 564         .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN,
 565         .get_rate       = local_return_parent_rate,
 566 };
 567 static struct clk clk_timer1 = {
 568         .parent         = &clk_pclk,
 569         .enable         = local_onoff_enable,
 570         .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
 571         .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
 572         .get_rate       = local_return_parent_rate,
 573 };
 574 static struct clk clk_timer2 = {
 575         .parent         = &clk_pclk,
 576         .enable         = local_onoff_enable,
 577         .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
 578         .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN,
 579         .get_rate       = local_return_parent_rate,
 580 };
 581 static struct clk clk_timer3 = {
 582         .parent         = &clk_pclk,
 583         .enable         = local_onoff_enable,
 584         .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
 585         .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
 586         .get_rate       = local_return_parent_rate,
 587 };
 588 static struct clk clk_wdt = {
 589         .parent         = &clk_pclk,
 590         .enable         = local_onoff_enable,
 591         .enable_reg     = LPC32XX_CLKPWR_TIMER_CLK_CTRL,
 592         .enable_mask    = LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
 593         .get_rate       = local_return_parent_rate,
 594 };
 595 static struct clk clk_vfp9 = {
 596         .parent         = &clk_pclk,
 597         .enable         = local_onoff_enable,
 598         .enable_reg     = LPC32XX_CLKPWR_DEBUG_CTRL,
 599         .enable_mask    = LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT,
 600         .get_rate       = local_return_parent_rate,
 601 };
 602 static struct clk clk_dma = {
 603         .parent         = &clk_hclk,
 604         .enable         = local_onoff_enable,
 605         .enable_reg     = LPC32XX_CLKPWR_DMA_CLK_CTRL,
 606         .enable_mask    = LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN,
 607         .get_rate       = local_return_parent_rate,
 608 };
 609
 610 static struct clk clk_uart3 = {
 611         .parent         = &clk_pclk,
 612         .enable         = local_onoff_enable,
 613         .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
 614         .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN,
 615         .get_rate       = local_return_parent_rate,
 616 };
 617
 618 static struct clk clk_uart4 = {
 619         .parent         = &clk_pclk,
 620         .enable         = local_onoff_enable,
 621         .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
 622         .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN,
 623         .get_rate       = local_return_parent_rate,
 624 };
 625
 626 static struct clk clk_uart5 = {
 627         .parent         = &clk_pclk,
 628         .enable         = local_onoff_enable,
 629         .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
 630         .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN,
 631         .get_rate       = local_return_parent_rate,
 632 };
 633
 634 static struct clk clk_uart6 = {
 635         .parent         = &clk_pclk,
 636         .enable         = local_onoff_enable,
 637         .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
 638         .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN,
 639         .get_rate       = local_return_parent_rate,
 640 };
 641
 642 static struct clk clk_i2c0 = {
 643         .parent         = &clk_hclk,
 644         .enable         = local_onoff_enable,
 645         .enable_reg     = LPC32XX_CLKPWR_I2C_CLK_CTRL,
 646         .enable_mask    = LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN,
 647         .get_rate       = local_return_parent_rate,
 648 };
 649
 650 static struct clk clk_i2c1 = {
 651         .parent         = &clk_hclk,
 652         .enable         = local_onoff_enable,
 653         .enable_reg     = LPC32XX_CLKPWR_I2C_CLK_CTRL,
 654         .enable_mask    = LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN,
 655         .get_rate       = local_return_parent_rate,
 656 };
 657
 658 static struct clk clk_i2c2 = {
 659         .parent         = &clk_pclk,
 660         .enable         = local_onoff_enable,
 661         .enable_reg     = io_p2v(LPC32XX_USB_BASE + 0xFF4),
 662         .enable_mask    = 0x4,
 663         .get_rate       = local_return_parent_rate,
 664 };
 665
 666 static struct clk clk_ssp0 = {
 667         .parent         = &clk_hclk,
 668         .enable         = local_onoff_enable,
 669         .enable_reg     = LPC32XX_CLKPWR_SSP_CLK_CTRL,
 670         .enable_mask    = LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN,
 671         .get_rate       = local_return_parent_rate,
 672 };
 673
 674 static struct clk clk_ssp1 = {
 675         .parent         = &clk_hclk,
 676         .enable         = local_onoff_enable,
 677         .enable_reg     = LPC32XX_CLKPWR_SSP_CLK_CTRL,
 678         .enable_mask    = LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN,
 679         .get_rate       = local_return_parent_rate,
 680 };
 681
 682 static struct clk clk_kscan = {
 683         .parent         = &osc_32KHz,
 684         .enable         = local_onoff_enable,
 685         .enable_reg     = LPC32XX_CLKPWR_KEY_CLK_CTRL,
 686         .enable_mask    = LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN,
 687         .get_rate       = local_return_parent_rate,
 688 };
 689
 690 static struct clk clk_nand = {
 691         .parent         = &clk_hclk,
 692         .enable         = local_onoff_enable,
 693         .enable_reg     = LPC32XX_CLKPWR_NAND_CLK_CTRL,
 694         .enable_mask    = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN,
 695         .get_rate       = local_return_parent_rate,
 696 };
 697
 698 static struct clk clk_i2s0 = {
 699         .parent         = &clk_hclk,
 700         .enable         = local_onoff_enable,
 701         .enable_reg     = LPC32XX_CLKPWR_I2S_CLK_CTRL,
 702         .enable_mask    = LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN,
 703         .get_rate       = local_return_parent_rate,
 704 };
 705
 706 static struct clk clk_i2s1 = {
 707         .parent         = &clk_hclk,
 708         .enable         = local_onoff_enable,
 709         .enable_reg     = LPC32XX_CLKPWR_I2S_CLK_CTRL,
 710         .enable_mask    = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN,
 711         .get_rate       = local_return_parent_rate,
 712 };
 713
 714 static struct clk clk_net = {
 715         .parent         = &clk_hclk,
 716         .enable         = local_onoff_enable,
 717         .enable_reg     = LPC32XX_CLKPWR_MACCLK_CTRL,
 718         .enable_mask    = (LPC32XX_CLKPWR_MACCTRL_DMACLK_EN |
 719                 LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN |
 720                 LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN),
 721         .get_rate       = local_return_parent_rate,
 722 };
 723
 724 static struct clk clk_rtc = {
 725         .parent         = &osc_32KHz,
 726         .rate           = 1, /* 1 Hz */
 727         .get_rate       = local_return_parent_rate,
 728 };
 729
 730 static struct clk clk_usbd = {
 731         .parent         = &clk_usbpll,
 732         .enable         = local_onoff_enable,
 733         .enable_reg     = LPC32XX_CLKPWR_USB_CTRL,
 734         .enable_mask    = LPC32XX_CLKPWR_USBCTRL_HCLK_EN,
 735         .get_rate       = local_return_parent_rate,
 736 };
 737
 738 static int tsc_onoff_enable(struct clk *clk, int enable)
 739 {
 740         u32 tmp;
 741
 742         /* Make sure 32KHz clock is the selected clock */
 743         tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
 744         tmp &= ~LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
 745         __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
 746
 747         if (enable == 0)
 748                 __raw_writel(0, clk->enable_reg);
 749         else
 750                 __raw_writel(clk->enable_mask, clk->enable_reg);
 751
 752         return 0;
 753 }
 754
 755 static struct clk clk_tsc = {
 756         .parent         = &osc_32KHz,
 757         .enable         = tsc_onoff_enable,
 758         .enable_reg     = LPC32XX_CLKPWR_ADC_CLK_CTRL,
 759         .enable_mask    = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
 760         .get_rate       = local_return_parent_rate,
 761 };
 762
 763 static int adc_onoff_enable(struct clk *clk, int enable)
 764 {
 765         u32 tmp;
 766         u32 divider;
 767
 768         /* Use PERIPH_CLOCK */
 769         tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
 770         tmp |= LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
 771         /*
 772          * Set clock divider so that we have equal to or less than
 773          * 4.5MHz clock at ADC
 774          */
 775         divider = clk->get_rate(clk) / 4500000 + 1;
 776         tmp |= divider;
 777         __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
 778
 779         /* synchronize rate of this clock w/ actual HW setting */
 780         clk->rate = clk->get_rate(clk->parent) / divider;
 781
 782         if (enable == 0)
 783                 __raw_writel(0, clk->enable_reg);
 784         else
 785                 __raw_writel(clk->enable_mask, clk->enable_reg);
 786
 787         return 0;
 788 }
 789
 790 static struct clk clk_adc = {
 791         .parent         = &clk_pclk,
 792         .enable         = adc_onoff_enable,
 793         .enable_reg     = LPC32XX_CLKPWR_ADC_CLK_CTRL,
 794         .enable_mask    = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
 795         .get_rate       = local_return_parent_rate,
 796 };
 797
 798 static int mmc_onoff_enable(struct clk *clk, int enable)
 799 {
 800         u32 tmp;
 801
 802         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
 803                 ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
 804
 805         /* If rate is 0, disable clock */
 806         if (enable != 0)
 807                 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
 808
 809         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
 810
 811         return 0;
 812 }
 813
 814 static unsigned long mmc_get_rate(struct clk *clk)
 815 {
 816         u32 div, rate, oldclk;
 817
 818         /* The MMC clock must be on when accessing an MMC register */
 819         oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
 820         __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
 821                 LPC32XX_CLKPWR_MS_CTRL);
 822         div = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
 823         __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
 824
 825         /* Get the parent clock rate */
 826         rate = clk->parent->get_rate(clk->parent);
 827
 828         /* Get the MMC controller clock divider value */
 829         div = div & LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
 830
 831         if (!div)
 832                 div = 1;
 833
 834         return rate / div;
 835 }
 836
 837 static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate)
 838 {
 839         unsigned long div, prate;
 840
 841         /* Get the parent clock rate */
 842         prate = clk->parent->get_rate(clk->parent);
 843
 844         if (rate >= prate)
 845                 return prate;
 846
 847         div = prate / rate;
 848         if (div > 0xf)
 849                 div = 0xf;
 850
 851         return prate / div;
 852 }
 853
 854 static int mmc_set_rate(struct clk *clk, unsigned long rate)
 855 {
 856         u32 oldclk, tmp;
 857         unsigned long prate, div, crate = mmc_round_rate(clk, rate);
 858
 859         prate = clk->parent->get_rate(clk->parent);
 860
 861         div = prate / crate;
 862
 863         /* The MMC clock must be on when accessing an MMC register */
 864         oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
 865         __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
 866                 LPC32XX_CLKPWR_MS_CTRL);
 867         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
 868                 ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
 869         tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div);
 870         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
 871
 872         __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
 873
 874         return 0;
 875 }
 876
 877 static struct clk clk_mmc = {
 878         .parent         = &clk_armpll,
 879         .set_rate       = mmc_set_rate,
 880         .get_rate       = mmc_get_rate,
 881         .round_rate     = mmc_round_rate,
 882         .enable         = mmc_onoff_enable,
 883         .enable_reg     = LPC32XX_CLKPWR_MS_CTRL,
 884         .enable_mask    = LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
 885 };
 886
 887 static unsigned long clcd_get_rate(struct clk *clk)
 888 {
 889         u32 tmp, div, rate, oldclk;
 890
 891         /* The LCD clock must be on when accessing an LCD register */
 892         oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
 893         __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
 894                 LPC32XX_CLKPWR_LCDCLK_CTRL);
 895         tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
 896         __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
 897
 898         rate = clk->parent->get_rate(clk->parent);
 899
 900         /* Only supports internal clocking */
 901         if (tmp & TIM2_BCD)
 902                 return rate;
 903
 904         div = (tmp & 0x1F) | ((tmp & 0xF8) >> 22);
 905         tmp = rate / (2 + div);
 906
 907         return tmp;
 908 }
 909
 910 static int clcd_set_rate(struct clk *clk, unsigned long rate)
 911 {
 912         u32 tmp, prate, div, oldclk;
 913
 914         /* The LCD clock must be on when accessing an LCD register */
 915         oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
 916         __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
 917                 LPC32XX_CLKPWR_LCDCLK_CTRL);
 918
 919         tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2)) | TIM2_BCD;
 920         prate = clk->parent->get_rate(clk->parent);
 921
 922         if (rate < prate) {
 923                 /* Find closest divider */
 924                 div = prate / rate;
 925                 if (div >= 2) {
 926                         div -= 2;
 927                         tmp &= ~TIM2_BCD;
 928                 }
 929
 930                 tmp &= ~(0xF800001F);
 931                 tmp |= (div & 0x1F);
 932                 tmp |= (((div >> 5) & 0x1F) << 27);
 933         }
 934
 935         __raw_writel(tmp, io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
 936         __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
 937
 938         return 0;
 939 }
 940
 941 static unsigned long clcd_round_rate(struct clk *clk, unsigned long rate)
 942 {
 943         u32 prate, div;
 944
 945         prate = clk->parent->get_rate(clk->parent);
 946
 947         if (rate >= prate)
 948                 rate = prate;
 949         else {
 950                 div = prate / rate;
 951                 if (div > 0x3ff)
 952                         div = 0x3ff;
 953
 954                 rate = prate / div;
 955         }
 956
 957         return rate;
 958 }
 959
 960 static struct clk clk_lcd = {
 961         .parent         = &clk_hclk,
 962         .set_rate       = clcd_set_rate,
 963         .get_rate       = clcd_get_rate,
 964         .round_rate     = clcd_round_rate,
 965         .enable         = local_onoff_enable,
 966         .enable_reg     = LPC32XX_CLKPWR_LCDCLK_CTRL,
 967         .enable_mask    = LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
 968 };
 969
 970 static void local_clk_disable(struct clk *clk)
 971 {
 972         /* Don't attempt to disable clock if it has no users */
 973         if (clk->usecount > 0) {
 974                 clk->usecount--;
 975
 976                 /* Only disable clock when it has no more users */
 977                 if ((clk->usecount == 0) && (clk->enable))
 978                         clk->enable(clk, 0);
 979
 980                 /* Check parent clocks, they may need to be disabled too */
 981                 if (clk->parent)
 982                         local_clk_disable(clk->parent);
 983         }
 984 }
 985
 986 static int local_clk_enable(struct clk *clk)
 987 {
 988         int ret = 0;
 989
 990         /* Enable parent clocks first and update use counts */
 991         if (clk->parent)
 992                 ret = local_clk_enable(clk->parent);
 993
 994         if (!ret) {
 995                 /* Only enable clock if it's currently disabled */
 996                 if ((clk->usecount == 0) && (clk->enable))
 997                         ret = clk->enable(clk, 1);
 998
 999                 if (!ret)
1000                         clk->usecount++;
1001                 else if (clk->parent)
1002                         local_clk_disable(clk->parent);
1003         }
1004
1005         return ret;
1006 }
1007
1008 /*
1009  * clk_enable - inform the system when the clock source should be running.
1010  */
1011 int clk_enable(struct clk *clk)
1012 {
1013         int ret;
1014         unsigned long flags;
1015
1016         spin_lock_irqsave(&global_clkregs_lock, flags);
1017         ret = local_clk_enable(clk);
1018         spin_unlock_irqrestore(&global_clkregs_lock, flags);
1019
1020         return ret;
1021 }
1022 EXPORT_SYMBOL(clk_enable);
1023
1024 /*
1025  * clk_disable - inform the system when the clock source is no longer required
1026  */
1027 void clk_disable(struct clk *clk)
1028 {
1029         unsigned long flags;
1030
1031         spin_lock_irqsave(&global_clkregs_lock, flags);
1032         local_clk_disable(clk);
1033         spin_unlock_irqrestore(&global_clkregs_lock, flags);
1034 }
1035 EXPORT_SYMBOL(clk_disable);
1036
1037 /*
1038  * clk_get_rate - obtain the current clock rate (in Hz) for a clock source
1039  */
1040 unsigned long clk_get_rate(struct clk *clk)
1041 {
1042         return clk->get_rate(clk);
1043 }
1044 EXPORT_SYMBOL(clk_get_rate);
1045
1046 /*
1047  * clk_set_rate - set the clock rate for a clock source
1048  */
1049 int clk_set_rate(struct clk *clk, unsigned long rate)
1050 {
1051         int ret = -EINVAL;
1052
1053         /*
1054          * Most system clocks can only be enabled or disabled, with
1055          * the actual rate set as part of the peripheral dividers
1056          * instead of high level clock control
1057          */
1058         if (clk->set_rate)
1059                 ret = clk->set_rate(clk, rate);
1060
1061         return ret;
1062 }
1063 EXPORT_SYMBOL(clk_set_rate);
1064
1065 /*
1066  * clk_round_rate - adjust a rate to the exact rate a clock can provide
1067  */
1068 long clk_round_rate(struct clk *clk, unsigned long rate)
1069 {
1070         if (clk->round_rate)
1071                 rate = clk->round_rate(clk, rate);
1072         else
1073                 rate = clk->get_rate(clk);
1074
1075         return rate;
1076 }
1077 EXPORT_SYMBOL(clk_round_rate);
1078
1079 /*
1080  * clk_set_parent - set the parent clock source for this clock
1081  */
1082 int clk_set_parent(struct clk *clk, struct clk *parent)
1083 {
1084         /* Clock re-parenting is not supported */
1085         return -EINVAL;
1086 }
1087 EXPORT_SYMBOL(clk_set_parent);
1088
1089 /*
1090  * clk_get_parent - get the parent clock source for this clock
1091  */
1092 struct clk *clk_get_parent(struct clk *clk)
1093 {
1094         return clk->parent;
1095 }
1096 EXPORT_SYMBOL(clk_get_parent);
1097
1098 static struct clk_lookup lookups[] = {
1099         CLKDEV_INIT(NULL, "osc_32KHz", &osc_32KHz),
1100         CLKDEV_INIT(NULL, "osc_pll397", &osc_pll397),
1101         CLKDEV_INIT(NULL, "osc_main", &osc_main),
1102         CLKDEV_INIT(NULL, "sys_ck", &clk_sys),
1103         CLKDEV_INIT(NULL, "arm_pll_ck", &clk_armpll),
1104         CLKDEV_INIT(NULL, "ck_pll5", &clk_usbpll),
1105         CLKDEV_INIT(NULL, "hclk_ck", &clk_hclk),
1106         CLKDEV_INIT(NULL, "pclk_ck", &clk_pclk),
1107         CLKDEV_INIT(NULL, "timer0_ck", &clk_timer0),
1108         CLKDEV_INIT(NULL, "timer1_ck", &clk_timer1),
1109         CLKDEV_INIT(NULL, "timer2_ck", &clk_timer2),
1110         CLKDEV_INIT(NULL, "timer3_ck", &clk_timer3),
1111         CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9),
1112         CLKDEV_INIT("pl08xdmac", NULL, &clk_dma),
1113         CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt),
1114         CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3),
1115         CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4),
1116         CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5),
1117         CLKDEV_INIT(NULL, "uart6_ck", &clk_uart6),
1118         CLKDEV_INIT("400a0000.i2c", NULL, &clk_i2c0),
1119         CLKDEV_INIT("400a8000.i2c", NULL, &clk_i2c1),
1120         CLKDEV_INIT("31020300.i2c", NULL, &clk_i2c2),
1121         CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0),
1122         CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1),
1123         CLKDEV_INIT("lpc32xx_keys.0", NULL, &clk_kscan),
1124         CLKDEV_INIT("lpc32xx-nand.0", "nand_ck", &clk_nand),
1125         CLKDEV_INIT("40048000.adc", NULL, &clk_adc),
1126         CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0),
1127         CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1),
1128         CLKDEV_INIT("40048000.tsc", NULL, &clk_tsc),
1129         CLKDEV_INIT("20098000.sd", NULL, &clk_mmc),
1130         CLKDEV_INIT("31060000.ethernet", NULL, &clk_net),
1131         CLKDEV_INIT("dev:clcd", NULL, &clk_lcd),
1132         CLKDEV_INIT("31020000.usbd", "ck_usbd", &clk_usbd),
1133         CLKDEV_INIT("lpc32xx_rtc", NULL, &clk_rtc),
1134 };
1135
1136 static int __init clk_init(void)
1137 {
1138         int i;
1139
1140         for (i = 0; i < ARRAY_SIZE(lookups); i++)
1141                 clkdev_add(&lookups[i]);
1142
1143         /*
1144          * Setup muxed SYSCLK for HCLK PLL base -this selects the
1145          * parent clock used for the ARM PLL and is used to derive
1146          * the many system clock rates in the device.
1147          */
1148         if (clk_is_sysclk_mainosc() != 0)
1149                 clk_sys.parent = &osc_main;
1150         else
1151                 clk_sys.parent = &osc_pll397;
1152
1153         clk_sys.rate = clk_sys.parent->rate;
1154
1155         /* Compute the current ARM PLL and USB PLL frequencies */
1156         local_update_armpll_rate();
1157
1158         /* Compute HCLK and PCLK bus rates */
1159         clk_hclk.rate = clk_hclk.parent->rate / clk_get_hclk_div();
1160         clk_pclk.rate = clk_pclk.parent->rate / clk_get_pclk_div();
1161
1162         /*
1163          * Enable system clocks - this step is somewhat formal, as the
1164          * clocks are already running, but it does get the clock data
1165          * inline with the actual system state. Never disable these
1166          * clocks as they will only stop if the system is going to sleep.
1167          * In that case, the chip/system power management functions will
1168          * handle clock gating.
1169          */
1170         if (clk_enable(&clk_hclk) || clk_enable(&clk_pclk))
1171                 printk(KERN_ERR "Error enabling system HCLK and PCLK\n");
1172
1173         /*
1174          * Timers 0 and 1 were enabled and are being used by the high
1175          * resolution tick function prior to this driver being initialized.
1176          * Tag them now as used.
1177          */
1178         if (clk_enable(&clk_timer0) || clk_enable(&clk_timer1))
1179                 printk(KERN_ERR "Error enabling timer tick clocks\n");
1180
1181         return 0;
1182 }
1183 core_initcall(clk_init);
1184