arch/arm/mach-k3/j721e_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * J721E: SoC specific initialization
   4  *
   5  * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
   6  *      Lokesh Vutla <lokeshvutla@ti.com>
   7  */
   8
   9 #include <init.h>
  10 #include <spl.h>
  11 #include <asm/io.h>
  12 #include <asm/armv7_mpu.h>
  13 #include <asm/arch/hardware.h>
  14 #include "sysfw-loader.h"
  15 #include "common.h"
  16 #include <linux/soc/ti/ti_sci_protocol.h>
  17 #include <dm.h>
  18 #include <dm/uclass-internal.h>
  19 #include <dm/pinctrl.h>
  20 #include <dm/root.h>
  21 #include <fdtdec.h>
  22 #include <mmc.h>
  23 #include <remoteproc.h>
  24
  25 #ifdef CONFIG_K3_LOAD_SYSFW
  26 struct fwl_data cbass_hc_cfg0_fwls[] = {
  27 #if defined(CONFIG_TARGET_J721E_R5_EVM)
  28         { "PCIE0_CFG", 2560, 8 },
  29         { "PCIE1_CFG", 2561, 8 },
  30         { "USB3SS0_CORE", 2568, 4 },
  31         { "USB3SS1_CORE", 2570, 4 },
  32         { "EMMC8SS0_CFG", 2576, 4 },
  33         { "UFS_HCI0_CFG", 2580, 4 },
  34         { "SERDES0", 2584, 1 },
  35         { "SERDES1", 2585, 1 },
  36 #elif defined(CONFIG_TARGET_J7200_R5_EVM)
  37         { "PCIE1_CFG", 2561, 7 },
  38 #endif
  39 }, cbass_hc0_fwls[] = {
  40 #if defined(CONFIG_TARGET_J721E_R5_EVM)
  41         { "PCIE0_HP", 2528, 24 },
  42         { "PCIE0_LP", 2529, 24 },
  43         { "PCIE1_HP", 2530, 24 },
  44         { "PCIE1_LP", 2531, 24 },
  45 #endif
  46 }, cbass_rc_cfg0_fwls[] = {
  47         { "EMMCSD4SS0_CFG", 2380, 4 },
  48 }, cbass_rc0_fwls[] = {
  49         { "GPMC0", 2310, 8 },
  50 }, infra_cbass0_fwls[] = {
  51         { "PLL_MMR0", 8, 26 },
  52         { "CTRL_MMR0", 9, 16 },
  53 }, mcu_cbass0_fwls[] = {
  54         { "MCU_R5FSS0_CORE0", 1024, 4 },
  55         { "MCU_R5FSS0_CORE0_CFG", 1025, 2 },
  56         { "MCU_R5FSS0_CORE1", 1028, 4 },
  57         { "MCU_FSS0_CFG", 1032, 12 },
  58         { "MCU_FSS0_S1", 1033, 8 },
  59         { "MCU_FSS0_S0", 1036, 8 },
  60         { "MCU_PSROM49152X32", 1048, 1 },
  61         { "MCU_MSRAM128KX64", 1050, 8 },
  62         { "MCU_CTRL_MMR0", 1200, 8 },
  63         { "MCU_PLL_MMR0", 1201, 3 },
  64         { "MCU_CPSW0", 1220, 2 },
  65 }, wkup_cbass0_fwls[] = {
  66         { "WKUP_CTRL_MMR0", 131, 16 },
  67 };
  68 #endif
  69
  70 static void ctrl_mmr_unlock(void)
  71 {
  72         /* Unlock all WKUP_CTRL_MMR0 module registers */
  73         mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
  74         mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
  75         mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
  76         mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
  77         mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
  78         mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
  79         mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
  80
  81         /* Unlock all MCU_CTRL_MMR0 module registers */
  82         mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
  83         mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
  84         mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
  85         mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
  86         mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
  87
  88         /* Unlock all CTRL_MMR0 module registers */
  89         mmr_unlock(CTRL_MMR0_BASE, 0);
  90         mmr_unlock(CTRL_MMR0_BASE, 1);
  91         mmr_unlock(CTRL_MMR0_BASE, 2);
  92         mmr_unlock(CTRL_MMR0_BASE, 3);
  93         mmr_unlock(CTRL_MMR0_BASE, 5);
  94         if (soc_is_j721e())
  95                 mmr_unlock(CTRL_MMR0_BASE, 6);
  96         mmr_unlock(CTRL_MMR0_BASE, 7);
  97 }
  98
  99 #if defined(CONFIG_K3_LOAD_SYSFW)
 100 void k3_mmc_stop_clock(void)
 101 {
 102         if (spl_boot_device() == BOOT_DEVICE_MMC1) {
 103                 struct mmc *mmc = find_mmc_device(0);
 104
 105                 if (!mmc)
 106                         return;
 107
 108                 mmc->saved_clock = mmc->clock;
 109                 mmc_set_clock(mmc, 0, true);
 110         }
 111 }
 112
 113 void k3_mmc_restart_clock(void)
 114 {
 115         if (spl_boot_device() == BOOT_DEVICE_MMC1) {
 116                 struct mmc *mmc = find_mmc_device(0);
 117
 118                 if (!mmc)
 119                         return;
 120
 121                 mmc_set_clock(mmc, mmc->saved_clock, false);
 122         }
 123 }
 124 #endif
 125
 126 /*
 127  * This uninitialized global variable would normal end up in the .bss section,
 128  * but the .bss is cleared between writing and reading this variable, so move
 129  * it to the .data section.
 130  */
 131 u32 bootindex __section(".data");
 132 static struct rom_extended_boot_data bootdata __section(".data");
 133
 134 static void store_boot_info_from_rom(void)
 135 {
 136         bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
 137         memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
 138                sizeof(struct rom_extended_boot_data));
 139 }
 140
 141 #ifdef CONFIG_SPL_OF_LIST
 142 void do_dt_magic(void)
 143 {
 144         int ret, rescan, mmc_dev = -1;
 145         static struct mmc *mmc;
 146
 147         /* Perform board detection */
 148         do_board_detect();
 149
 150         /*
 151          * Board detection has been done.
 152          * Let us see if another dtb wouldn't be a better match
 153          * for our board
 154          */
 155         if (IS_ENABLED(CONFIG_CPU_V7R)) {
 156                 ret = fdtdec_resetup(&rescan);
 157                 if (!ret && rescan) {
 158                         dm_uninit();
 159                         dm_init_and_scan(true);
 160                 }
 161         }
 162
 163         /*
 164          * Because of multi DTB configuration, the MMC device has
 165          * to be re-initialized after reconfiguring FDT inorder to
 166          * boot from MMC. Do this when boot mode is MMC and ROM has
 167          * not loaded SYSFW.
 168          */
 169         switch (spl_boot_device()) {
 170         case BOOT_DEVICE_MMC1:
 171                 mmc_dev = 0;
 172                 break;
 173         case BOOT_DEVICE_MMC2:
 174         case BOOT_DEVICE_MMC2_2:
 175                 mmc_dev = 1;
 176                 break;
 177         }
 178
 179         if (mmc_dev > 0 && !is_rom_loaded_sysfw(&bootdata)) {
 180                 ret = mmc_init_device(mmc_dev);
 181                 if (!ret) {
 182                         mmc = find_mmc_device(mmc_dev);
 183                         if (mmc) {
 184                                 ret = mmc_init(mmc);
 185                                 if (ret) {
 186                                         printf("mmc init failed with error: %d\n", ret);
 187                                 }
 188                         }
 189                 }
 190         }
 191 }
 192 #endif
 193
 194 void board_init_f(ulong dummy)
 195 {
 196 #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
 197         struct udevice *dev;
 198         int ret;
 199 #endif
 200         /*
 201          * Cannot delay this further as there is a chance that
 202          * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
 203          */
 204         store_boot_info_from_rom();
 205
 206         /* Make all control module registers accessible */
 207         ctrl_mmr_unlock();
 208
 209 #ifdef CONFIG_CPU_V7R
 210         disable_linefill_optimization();
 211         setup_k3_mpu_regions();
 212 #endif
 213
 214         /* Init DM early */
 215         spl_early_init();
 216
 217 #ifdef CONFIG_K3_LOAD_SYSFW
 218         /*
 219          * Process pinctrl for the serial0 a.k.a. MCU_UART0 module and continue
 220          * regardless of the result of pinctrl. Do this without probing the
 221          * device, but instead by searching the device that would request the
 222          * given sequence number if probed. The UART will be used by the system
 223          * firmware (SYSFW) image for various purposes and SYSFW depends on us
 224          * to initialize its pin settings.
 225          */
 226         ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
 227         if (!ret)
 228                 pinctrl_select_state(dev, "default");
 229
 230         /*
 231          * Force probe of clk_k3 driver here to ensure basic default clock
 232          * configuration is always done.
 233          */
 234         if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
 235                 ret = uclass_get_device_by_driver(UCLASS_CLK,
 236                                                   DM_DRIVER_GET(ti_clk),
 237                                                   &dev);
 238                 if (ret)
 239                         panic("Failed to initialize clk-k3!\n");
 240         }
 241
 242         /*
 243          * Load, start up, and configure system controller firmware. Provide
 244          * the U-Boot console init function to the SYSFW post-PM configuration
 245          * callback hook, effectively switching on (or over) the console
 246          * output.
 247          */
 248         k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
 249                         k3_mmc_stop_clock, k3_mmc_restart_clock);
 250
 251 #ifdef CONFIG_SPL_OF_LIST
 252         do_dt_magic();
 253 #endif
 254
 255         /* Prepare console output */
 256         preloader_console_init();
 257
 258         /* Disable ROM configured firewalls right after loading sysfw */
 259         remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
 260         remove_fwl_configs(cbass_hc0_fwls, ARRAY_SIZE(cbass_hc0_fwls));
 261         remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
 262         remove_fwl_configs(cbass_rc0_fwls, ARRAY_SIZE(cbass_rc0_fwls));
 263         remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
 264         remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
 265         remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
 266 #else
 267         /* Prepare console output */
 268         preloader_console_init();
 269 #endif
 270
 271         /* Output System Firmware version info */
 272         k3_sysfw_print_ver();
 273
 274         /* Perform board detection */
 275         do_board_detect();
 276
 277 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
 278         ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
 279                                           &dev);
 280         if (ret)
 281                 printf("AVS init failed: %d\n", ret);
 282 #endif
 283
 284 #if defined(CONFIG_K3_J721E_DDRSS)
 285         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 286         if (ret)
 287                 panic("DRAM init failed: %d\n", ret);
 288 #endif
 289         spl_enable_dcache();
 290 }
 291
 292 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
 293 {
 294         switch (boot_device) {
 295         case BOOT_DEVICE_MMC1:
 296                 return (spl_mmc_emmc_boot_partition(mmc) ? MMCSD_MODE_EMMCBOOT : MMCSD_MODE_FS);
 297         case BOOT_DEVICE_MMC2:
 298                 return MMCSD_MODE_FS;
 299         default:
 300                 return MMCSD_MODE_RAW;
 301         }
 302 }
 303
 304 static u32 __get_backup_bootmedia(u32 main_devstat)
 305 {
 306         u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
 307                         MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
 308
 309         switch (bkup_boot) {
 310         case BACKUP_BOOT_DEVICE_USB:
 311                 return BOOT_DEVICE_DFU;
 312         case BACKUP_BOOT_DEVICE_UART:
 313                 return BOOT_DEVICE_UART;
 314         case BACKUP_BOOT_DEVICE_ETHERNET:
 315                 return BOOT_DEVICE_ETHERNET;
 316         case BACKUP_BOOT_DEVICE_MMC2:
 317         {
 318                 u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
 319                             MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
 320                 if (port == 0x0)
 321                         return BOOT_DEVICE_MMC1;
 322                 return BOOT_DEVICE_MMC2;
 323         }
 324         case BACKUP_BOOT_DEVICE_SPI:
 325                 return BOOT_DEVICE_SPI;
 326         case BACKUP_BOOT_DEVICE_I2C:
 327                 return BOOT_DEVICE_I2C;
 328         }
 329
 330         return BOOT_DEVICE_RAM;
 331 }
 332
 333 static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
 334 {
 335
 336         u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
 337                         WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
 338
 339         bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
 340                         BOOT_MODE_B_SHIFT;
 341
 342         if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
 343                 bootmode = BOOT_DEVICE_SPI;
 344
 345         if (bootmode == BOOT_DEVICE_MMC2) {
 346                 u32 port = (main_devstat &
 347                             MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
 348                            MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
 349                 if (port == 0x0)
 350                         bootmode = BOOT_DEVICE_MMC1;
 351         }
 352
 353         return bootmode;
 354 }
 355
 356 u32 spl_spi_boot_bus(void)
 357 {
 358         u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
 359         u32 main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 360         u32 bootmode = ((wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
 361                         WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT) |
 362                         ((main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) << BOOT_MODE_B_SHIFT);
 363
 364         return (bootmode == BOOT_DEVICE_QSPI) ? 1 : 0;
 365 }
 366
 367 u32 spl_boot_device(void)
 368 {
 369         u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
 370         u32 main_devstat;
 371
 372         if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
 373                 printf("ERROR: MCU only boot is not yet supported\n");
 374                 return BOOT_DEVICE_RAM;
 375         }
 376
 377         /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
 378         main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 379
 380         if (bootindex == K3_PRIMARY_BOOTMODE)
 381                 return __get_primary_bootmedia(main_devstat, wkup_devstat);
 382         else
 383                 return __get_backup_bootmedia(main_devstat);
 384 }