1 // SPDX-License-Identifier: GPL-2.0+
3 * J721E: SoC specific initialization
5 * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
13 #include <asm/armv7_mpu.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sysfw-loader.h>
17 #include <asm/arch/sys_proto.h>
18 #include <linux/soc/ti/ti_sci_protocol.h>
20 #include <dm/uclass-internal.h>
21 #include <dm/pinctrl.h>
23 #include <remoteproc.h>
25 #ifdef CONFIG_SPL_BUILD
26 #ifdef CONFIG_K3_LOAD_SYSFW
27 #ifdef CONFIG_TI_SECURE_DEVICE
28 struct fwl_data cbass_hc_cfg0_fwls[] = {
29 { "PCIE0_CFG", 2560, 8 },
30 { "PCIE1_CFG", 2561, 8 },
31 { "USB3SS0_CORE", 2568, 4 },
32 { "USB3SS1_CORE", 2570, 4 },
33 { "EMMC8SS0_CFG", 2576, 4 },
34 { "UFS_HCI0_CFG", 2580, 4 },
35 { "SERDES0", 2584, 1 },
36 { "SERDES1", 2585, 1 },
37 }, cbass_hc0_fwls[] = {
38 { "PCIE0_HP", 2528, 24 },
39 { "PCIE0_LP", 2529, 24 },
40 { "PCIE1_HP", 2530, 24 },
41 { "PCIE1_LP", 2531, 24 },
42 }, cbass_rc_cfg0_fwls[] = {
43 { "EMMCSD4SS0_CFG", 2380, 4 },
44 }, cbass_rc0_fwls[] = {
46 }, infra_cbass0_fwls[] = {
47 { "PLL_MMR0", 8, 26 },
48 { "CTRL_MMR0", 9, 16 },
49 }, mcu_cbass0_fwls[] = {
50 { "MCU_R5FSS0_CORE0", 1024, 4 },
51 { "MCU_R5FSS0_CORE0_CFG", 1025, 2 },
52 { "MCU_R5FSS0_CORE1", 1028, 4 },
53 { "MCU_FSS0_CFG", 1032, 12 },
54 { "MCU_FSS0_S1", 1033, 8 },
55 { "MCU_FSS0_S0", 1036, 8 },
56 { "MCU_PSROM49152X32", 1048, 1 },
57 { "MCU_MSRAM128KX64", 1050, 8 },
58 { "MCU_CTRL_MMR0", 1200, 8 },
59 { "MCU_PLL_MMR0", 1201, 3 },
60 { "MCU_CPSW0", 1220, 2 },
61 }, wkup_cbass0_fwls[] = {
62 { "WKUP_CTRL_MMR0", 131, 16 },
67 static void mmr_unlock(u32 base, u32 partition)
69 /* Translate the base address */
70 phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
72 /* Unlock the requested partition if locked using two-step sequence */
73 writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
74 writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
77 static void ctrl_mmr_unlock(void)
79 /* Unlock all WKUP_CTRL_MMR0 module registers */
80 mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
81 mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
82 mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
83 mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
84 mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
85 mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
86 mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
88 /* Unlock all MCU_CTRL_MMR0 module registers */
89 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
90 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
91 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
92 mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
93 mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
95 /* Unlock all CTRL_MMR0 module registers */
96 mmr_unlock(CTRL_MMR0_BASE, 0);
97 mmr_unlock(CTRL_MMR0_BASE, 1);
98 mmr_unlock(CTRL_MMR0_BASE, 2);
99 mmr_unlock(CTRL_MMR0_BASE, 3);
100 mmr_unlock(CTRL_MMR0_BASE, 4);
101 mmr_unlock(CTRL_MMR0_BASE, 5);
102 mmr_unlock(CTRL_MMR0_BASE, 6);
103 mmr_unlock(CTRL_MMR0_BASE, 7);
106 #if defined(CONFIG_K3_LOAD_SYSFW)
107 void k3_mmc_stop_clock(void)
109 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
110 struct mmc *mmc = find_mmc_device(0);
115 mmc->saved_clock = mmc->clock;
116 mmc_set_clock(mmc, 0, true);
120 void k3_mmc_restart_clock(void)
122 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
123 struct mmc *mmc = find_mmc_device(0);
128 mmc_set_clock(mmc, mmc->saved_clock, false);
134 * This uninitialized global variable would normal end up in the .bss section,
135 * but the .bss is cleared between writing and reading this variable, so move
136 * it to the .data section.
138 u32 bootindex __attribute__((section(".data")));
140 static void store_boot_index_from_rom(void)
142 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
145 void board_init_f(ulong dummy)
147 #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
152 * Cannot delay this further as there is a chance that
153 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
155 store_boot_index_from_rom();
157 /* Make all control module registers accessible */
160 #ifdef CONFIG_CPU_V7R
161 disable_linefill_optimization();
162 setup_k3_mpu_regions();
168 #ifdef CONFIG_K3_LOAD_SYSFW
170 * Process pinctrl for the serial0 a.k.a. MCU_UART0 module and continue
171 * regardless of the result of pinctrl. Do this without probing the
172 * device, but instead by searching the device that would request the
173 * given sequence number if probed. The UART will be used by the system
174 * firmware (SYSFW) image for various purposes and SYSFW depends on us
175 * to initialize its pin settings.
177 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
179 pinctrl_select_state(dev, "default");
182 * Load, start up, and configure system controller firmware. Provide
183 * the U-Boot console init function to the SYSFW post-PM configuration
184 * callback hook, effectively switching on (or over) the console
187 k3_sysfw_loader(k3_mmc_stop_clock, k3_mmc_restart_clock);
189 /* Prepare console output */
190 preloader_console_init();
192 /* Disable ROM configured firewalls right after loading sysfw */
193 #ifdef CONFIG_TI_SECURE_DEVICE
194 remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
195 remove_fwl_configs(cbass_hc0_fwls, ARRAY_SIZE(cbass_hc0_fwls));
196 remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
197 remove_fwl_configs(cbass_rc0_fwls, ARRAY_SIZE(cbass_rc0_fwls));
198 remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
199 remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
200 remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
203 /* Prepare console output */
204 preloader_console_init();
207 /* Output System Firmware version info */
208 k3_sysfw_print_ver();
210 /* Perform EEPROM-based board detection */
213 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
214 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
217 printf("AVS init failed: %d\n", ret);
220 #if defined(CONFIG_K3_J721E_DDRSS)
221 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
223 panic("DRAM init failed: %d\n", ret);
227 u32 spl_mmc_boot_mode(const u32 boot_device)
229 switch (boot_device) {
230 case BOOT_DEVICE_MMC1:
231 return MMCSD_MODE_EMMCBOOT;
232 case BOOT_DEVICE_MMC2:
233 return MMCSD_MODE_FS;
235 return MMCSD_MODE_RAW;
239 static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
242 u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
243 WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
245 bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
248 if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
249 bootmode = BOOT_DEVICE_SPI;
251 if (bootmode == BOOT_DEVICE_MMC2) {
252 u32 port = (main_devstat &
253 MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
254 MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
256 bootmode = BOOT_DEVICE_MMC1;
262 u32 spl_boot_device(void)
264 u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
267 if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
268 printf("ERROR: MCU only boot is not yet supported\n");
269 return BOOT_DEVICE_RAM;
272 /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
273 main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
275 /* ToDo: Add support for backup boot media */
276 return __get_primary_bootmedia(main_devstat, wkup_devstat);
280 #ifdef CONFIG_SYS_K3_SPL_ATF
282 #define J721E_DEV_MCU_RTI0 262
283 #define J721E_DEV_MCU_RTI1 263
284 #define J721E_DEV_MCU_ARMSS0_CPU0 250
285 #define J721E_DEV_MCU_ARMSS0_CPU1 251
287 void release_resources_for_core_shutdown(void)
289 struct ti_sci_handle *ti_sci;
290 struct ti_sci_dev_ops *dev_ops;
291 struct ti_sci_proc_ops *proc_ops;
295 const u32 put_device_ids[] = {
300 ti_sci = get_ti_sci_handle();
301 dev_ops = &ti_sci->ops.dev_ops;
302 proc_ops = &ti_sci->ops.proc_ops;
304 /* Iterate through list of devices to put (shutdown) */
305 for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
306 u32 id = put_device_ids[i];
308 ret = dev_ops->put_device(ti_sci, id);
310 panic("Failed to put device %u (%d)\n", id, ret);
313 const u32 put_core_ids[] = {
314 J721E_DEV_MCU_ARMSS0_CPU1,
315 J721E_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
318 /* Iterate through list of cores to put (shutdown) */
319 for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
320 u32 id = put_core_ids[i];
323 * Queue up the core shutdown request. Note that this call
324 * needs to be followed up by an actual invocation of an WFE
325 * or WFI CPU instruction.
327 ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
329 panic("Failed sending core %u shutdown message (%d)\n",
335 #ifdef CONFIG_SYS_K3_SPL_ATF
336 void start_non_linux_remote_cores(void)
341 size = load_firmware("name_mainr5f0_0fw", "addr_mainr5f0_0load",
346 /* assuming remoteproc 2 is aliased for the needed remotecore */
347 ret = rproc_load(2, loadaddr, size);
349 printf("Firmware failed to start on rproc (%d)\n", ret);
353 ret = rproc_start(2);
355 printf("Firmware init failed on rproc (%d)\n", ret);
359 printf("Remoteproc 2 started successfully\n");