1 // SPDX-License-Identifier: GPL-2.0+
3 * J721E: SoC specific initialization
5 * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
12 #include <asm/armv7_mpu.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/sysfw-loader.h>
16 #include <asm/arch/sys_proto.h>
17 #include <linux/soc/ti/ti_sci_protocol.h>
19 #include <dm/uclass-internal.h>
20 #include <dm/pinctrl.h>
22 #ifdef CONFIG_SPL_BUILD
23 static void mmr_unlock(u32 base, u32 partition)
25 /* Translate the base address */
26 phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
28 /* Unlock the requested partition if locked using two-step sequence */
29 writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
30 writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
33 static void ctrl_mmr_unlock(void)
35 /* Unlock all WKUP_CTRL_MMR0 module registers */
36 mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
37 mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
38 mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
39 mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
40 mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
41 mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
42 mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
44 /* Unlock all MCU_CTRL_MMR0 module registers */
45 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
46 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
47 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
48 mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
49 mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
51 /* Unlock all CTRL_MMR0 module registers */
52 mmr_unlock(CTRL_MMR0_BASE, 0);
53 mmr_unlock(CTRL_MMR0_BASE, 1);
54 mmr_unlock(CTRL_MMR0_BASE, 2);
55 mmr_unlock(CTRL_MMR0_BASE, 3);
56 mmr_unlock(CTRL_MMR0_BASE, 4);
57 mmr_unlock(CTRL_MMR0_BASE, 5);
58 mmr_unlock(CTRL_MMR0_BASE, 6);
59 mmr_unlock(CTRL_MMR0_BASE, 7);
63 * This uninitialized global variable would normal end up in the .bss section,
64 * but the .bss is cleared between writing and reading this variable, so move
65 * it to the .data section.
67 u32 bootindex __attribute__((section(".data")));
69 static void store_boot_index_from_rom(void)
71 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
74 void board_init_f(ulong dummy)
76 #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
81 * Cannot delay this further as there is a chance that
82 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
84 store_boot_index_from_rom();
86 /* Make all control module registers accessible */
90 setup_k3_mpu_regions();
96 #ifdef CONFIG_K3_LOAD_SYSFW
98 * Process pinctrl for the serial0 a.k.a. MCU_UART0 module and continue
99 * regardless of the result of pinctrl. Do this without probing the
100 * device, but instead by searching the device that would request the
101 * given sequence number if probed. The UART will be used by the system
102 * firmware (SYSFW) image for various purposes and SYSFW depends on us
103 * to initialize its pin settings.
105 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
107 pinctrl_select_state(dev, "default");
110 * Load, start up, and configure system controller firmware. Provide
111 * the U-Boot console init function to the SYSFW post-PM configuration
112 * callback hook, effectively switching on (or over) the console
115 k3_sysfw_loader(preloader_console_init);
117 /* Prepare console output */
118 preloader_console_init();
121 #if defined(CONFIG_K3_J721E_DDRSS)
122 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
124 panic("DRAM init failed: %d\n", ret);
128 u32 spl_boot_mode(const u32 boot_device)
130 switch (boot_device) {
131 case BOOT_DEVICE_MMC1:
132 return MMCSD_MODE_EMMCBOOT;
133 case BOOT_DEVICE_MMC2:
134 return MMCSD_MODE_FS;
136 return MMCSD_MODE_RAW;
140 static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
143 u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
144 WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
146 bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
149 if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
150 bootmode = BOOT_DEVICE_SPI;
152 if (bootmode == BOOT_DEVICE_MMC2) {
153 u32 port = (main_devstat &
154 MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
155 MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
157 bootmode = BOOT_DEVICE_MMC1;
163 u32 spl_boot_device(void)
165 u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
168 if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
169 printf("ERROR: MCU only boot is not yet supported\n");
170 return BOOT_DEVICE_RAM;
173 /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
174 main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
176 /* ToDo: Add support for backup boot media */
177 return __get_primary_bootmedia(main_devstat, wkup_devstat);
181 #ifdef CONFIG_SYS_K3_SPL_ATF
183 #define J721E_DEV_MCU_RTI0 262
184 #define J721E_DEV_MCU_RTI1 263
185 #define J721E_DEV_MCU_ARMSS0_CPU0 250
186 #define J721E_DEV_MCU_ARMSS0_CPU1 251
188 void release_resources_for_core_shutdown(void)
190 struct ti_sci_handle *ti_sci;
191 struct ti_sci_dev_ops *dev_ops;
192 struct ti_sci_proc_ops *proc_ops;
196 const u32 put_device_ids[] = {
201 ti_sci = get_ti_sci_handle();
202 dev_ops = &ti_sci->ops.dev_ops;
203 proc_ops = &ti_sci->ops.proc_ops;
205 /* Iterate through list of devices to put (shutdown) */
206 for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
207 u32 id = put_device_ids[i];
209 ret = dev_ops->put_device(ti_sci, id);
211 panic("Failed to put device %u (%d)\n", id, ret);
214 const u32 put_core_ids[] = {
215 J721E_DEV_MCU_ARMSS0_CPU1,
216 J721E_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
219 /* Iterate through list of cores to put (shutdown) */
220 for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
221 u32 id = put_core_ids[i];
224 * Queue up the core shutdown request. Note that this call
225 * needs to be followed up by an actual invocation of an WFE
226 * or WFI CPU instruction.
228 ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
230 panic("Failed sending core %u shutdown message (%d)\n",