2 * arch/arm/mach-ixp4xx/include/mach/io.h
4 * Author: Deepak Saxena <dsaxena@plexity.net>
6 * Copyright (C) 2002-2005 MontaVista Software, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ASM_ARM_ARCH_IO_H
14 #define __ASM_ARM_ARCH_IO_H
16 #include <linux/bitops.h>
18 #include <mach/hardware.h>
20 #define IO_SPACE_LIMIT 0x0000ffff
22 extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
23 extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
27 * IXP4xx provides two methods of accessing PCI memory space:
29 * 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB).
30 * To access PCI via this space, we simply ioremap() the BAR
31 * into the kernel and we can use the standard read[bwl]/write[bwl]
32 * macros. This is the preffered method due to speed but it
33 * limits the system to just 64MB of PCI memory. This can be
34 * problematic if using video cards and other memory-heavy targets.
36 * 2) If > 64MB of memory space is required, the IXP4xx can use indirect
37 * registers to access the whole 4 GB of PCI memory space (as we do below
38 * for I/O transactions). This allows currently for up to 1 GB (0x10000000
39 * to 0x4FFFFFFF) of memory on the bus. The disadvantage of this is that
40 * every PCI access requires three local register accesses plus a spinlock,
41 * but in some cases the performance hit is acceptable. In addition, you
42 * cannot mmap() PCI devices in this case.
44 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
46 #define __mem_pci(a) (a)
51 * In the case of using indirect PCI, we simply return the actual PCI
52 * address and our read/write implementation use that to drive the
53 * access registers. If something outside of PCI is ioremap'd, we
54 * fallback to the default.
57 static inline int is_pci_memory(u32 addr)
59 return (addr >= PCIBIOS_MIN_MEM) && (addr <= 0x4FFFFFFF);
62 static inline void __iomem * __indirect_ioremap(unsigned long addr, size_t size,
65 if (!is_pci_memory(addr))
66 return __arm_ioremap(addr, size, mtype);
68 return (void __iomem *)addr;
71 static inline void __indirect_iounmap(void __iomem *addr)
73 if (!is_pci_memory((__force u32)addr))
77 #define __arch_ioremap(a, s, f) __indirect_ioremap(a, s, f)
78 #define __arch_iounmap(a) __indirect_iounmap(a)
80 #define writeb(v, p) __indirect_writeb(v, p)
81 #define writew(v, p) __indirect_writew(v, p)
82 #define writel(v, p) __indirect_writel(v, p)
84 #define writesb(p, v, l) __indirect_writesb(p, v, l)
85 #define writesw(p, v, l) __indirect_writesw(p, v, l)
86 #define writesl(p, v, l) __indirect_writesl(p, v, l)
88 #define readb(p) __indirect_readb(p)
89 #define readw(p) __indirect_readw(p)
90 #define readl(p) __indirect_readl(p)
92 #define readsb(p, v, l) __indirect_readsb(p, v, l)
93 #define readsw(p, v, l) __indirect_readsw(p, v, l)
94 #define readsl(p, v, l) __indirect_readsl(p, v, l)
96 static inline void __indirect_writeb(u8 value, volatile void __iomem *p)
99 u32 n, byte_enables, data;
101 if (!is_pci_memory(addr)) {
102 __raw_writeb(value, addr);
107 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
108 data = value << (8*n);
109 ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
112 static inline void __indirect_writesb(volatile void __iomem *bus_addr,
113 const u8 *vaddr, int count)
116 writeb(*vaddr++, bus_addr);
119 static inline void __indirect_writew(u16 value, volatile void __iomem *p)
122 u32 n, byte_enables, data;
124 if (!is_pci_memory(addr)) {
125 __raw_writew(value, addr);
130 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
131 data = value << (8*n);
132 ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
135 static inline void __indirect_writesw(volatile void __iomem *bus_addr,
136 const u16 *vaddr, int count)
139 writew(*vaddr++, bus_addr);
142 static inline void __indirect_writel(u32 value, volatile void __iomem *p)
144 u32 addr = (__force u32)p;
146 if (!is_pci_memory(addr)) {
147 __raw_writel(value, p);
151 ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value);
154 static inline void __indirect_writesl(volatile void __iomem *bus_addr,
155 const u32 *vaddr, int count)
158 writel(*vaddr++, bus_addr);
161 static inline unsigned char __indirect_readb(const volatile void __iomem *p)
164 u32 n, byte_enables, data;
166 if (!is_pci_memory(addr))
167 return __raw_readb(addr);
170 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
171 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
174 return data >> (8*n);
177 static inline void __indirect_readsb(const volatile void __iomem *bus_addr,
178 u8 *vaddr, u32 count)
181 *vaddr++ = readb(bus_addr);
184 static inline unsigned short __indirect_readw(const volatile void __iomem *p)
187 u32 n, byte_enables, data;
189 if (!is_pci_memory(addr))
190 return __raw_readw(addr);
193 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
194 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
200 static inline void __indirect_readsw(const volatile void __iomem *bus_addr,
201 u16 *vaddr, u32 count)
204 *vaddr++ = readw(bus_addr);
207 static inline unsigned long __indirect_readl(const volatile void __iomem *p)
209 u32 addr = (__force u32)p;
212 if (!is_pci_memory(addr))
213 return __raw_readl(p);
215 if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
221 static inline void __indirect_readsl(const volatile void __iomem *bus_addr,
222 u32 *vaddr, u32 count)
225 *vaddr++ = readl(bus_addr);
230 * We can use the built-in functions b/c they end up calling writeb/readb
232 #define memset_io(c,v,l) _memset_io((c),(v),(l))
233 #define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l))
234 #define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l))
236 #endif /* CONFIG_IXP4XX_INDIRECT_PCI */
240 #define __io(v) __typesafe_io(v)
245 * IXP4xx does not have a transparent cpu -> PCI I/O translation
246 * window. Instead, it has a set of registers that must be tweaked
247 * with the proper byte lanes, command types, and address for the
248 * transaction. This means that we need to override the default
252 static inline void outb(u8 value, u32 addr)
254 u32 n, byte_enables, data;
256 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
257 data = value << (8*n);
258 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
261 static inline void outsb(u32 io_addr, const u8 *vaddr, u32 count)
264 outb(*vaddr++, io_addr);
267 static inline void outw(u16 value, u32 addr)
269 u32 n, byte_enables, data;
271 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
272 data = value << (8*n);
273 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
276 static inline void outsw(u32 io_addr, const u16 *vaddr, u32 count)
279 outw(cpu_to_le16(*vaddr++), io_addr);
282 static inline void outl(u32 value, u32 addr)
284 ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
287 static inline void outsl(u32 io_addr, const u32 *vaddr, u32 count)
290 outl(cpu_to_le32(*vaddr++), io_addr);
293 static inline u8 inb(u32 addr)
295 u32 n, byte_enables, data;
297 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
298 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
301 return data >> (8*n);
304 static inline void insb(u32 io_addr, u8 *vaddr, u32 count)
307 *vaddr++ = inb(io_addr);
310 static inline u16 inw(u32 addr)
312 u32 n, byte_enables, data;
314 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
315 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
321 static inline void insw(u32 io_addr, u16 *vaddr, u32 count)
324 *vaddr++ = le16_to_cpu(inw(io_addr));
327 static inline u32 inl(u32 addr)
330 if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data))
336 static inline void insl(u32 io_addr, u32 *vaddr, u32 count)
339 *vaddr++ = le32_to_cpu(inl(io_addr));
342 #define PIO_OFFSET 0x10000UL
343 #define PIO_MASK 0x0ffffUL
345 #define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \
346 ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
348 #define ioread8(p) ioread8(p)
349 static inline unsigned int ioread8(const void __iomem *addr)
351 unsigned long port = (unsigned long __force)addr;
352 if (__is_io_address(port))
353 return (unsigned int)inb(port & PIO_MASK);
355 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
356 return (unsigned int)__raw_readb(port);
358 return (unsigned int)__indirect_readb(addr);
362 #define ioread8_rep(p, v, c) ioread8_rep(p, v, c)
363 static inline void ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
365 unsigned long port = (unsigned long __force)addr;
366 if (__is_io_address(port))
367 insb(port & PIO_MASK, vaddr, count);
369 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
370 __raw_readsb(addr, vaddr, count);
372 __indirect_readsb(addr, vaddr, count);
376 #define ioread16(p) ioread16(p)
377 static inline unsigned int ioread16(const void __iomem *addr)
379 unsigned long port = (unsigned long __force)addr;
380 if (__is_io_address(port))
381 return (unsigned int)inw(port & PIO_MASK);
383 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
384 return le16_to_cpu(__raw_readw((u32)port));
386 return (unsigned int)__indirect_readw(addr);
390 #define ioread16_rep(p, v, c) ioread16_rep(p, v, c)
391 static inline void ioread16_rep(const void __iomem *addr, void *vaddr,
394 unsigned long port = (unsigned long __force)addr;
395 if (__is_io_address(port))
396 insw(port & PIO_MASK, vaddr, count);
398 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
399 __raw_readsw(addr, vaddr, count);
401 __indirect_readsw(addr, vaddr, count);
405 #define ioread32(p) ioread32(p)
406 static inline unsigned int ioread32(const void __iomem *addr)
408 unsigned long port = (unsigned long __force)addr;
409 if (__is_io_address(port))
410 return (unsigned int)inl(port & PIO_MASK);
412 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
413 return le32_to_cpu((__force __le32)__raw_readl(addr));
415 return (unsigned int)__indirect_readl(addr);
420 #define ioread32_rep(p, v, c) ioread32_rep(p, v, c)
421 static inline void ioread32_rep(const void __iomem *addr, void *vaddr,
424 unsigned long port = (unsigned long __force)addr;
425 if (__is_io_address(port))
426 insl(port & PIO_MASK, vaddr, count);
428 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
429 __raw_readsl(addr, vaddr, count);
431 __indirect_readsl(addr, vaddr, count);
435 #define iowrite8(v, p) iowrite8(v, p)
436 static inline void iowrite8(u8 value, void __iomem *addr)
438 unsigned long port = (unsigned long __force)addr;
439 if (__is_io_address(port))
440 outb(value, port & PIO_MASK);
442 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
443 __raw_writeb(value, port);
445 __indirect_writeb(value, addr);
449 #define iowrite8_rep(p, v, c) iowrite8_rep(p, v, c)
450 static inline void iowrite8_rep(void __iomem *addr, const void *vaddr,
453 unsigned long port = (unsigned long __force)addr;
454 if (__is_io_address(port))
455 outsb(port & PIO_MASK, vaddr, count);
457 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
458 __raw_writesb(addr, vaddr, count);
460 __indirect_writesb(addr, vaddr, count);
464 #define iowrite16(v, p) iowrite16(v, p)
465 static inline void iowrite16(u16 value, void __iomem *addr)
467 unsigned long port = (unsigned long __force)addr;
468 if (__is_io_address(port))
469 outw(value, port & PIO_MASK);
471 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
472 __raw_writew(cpu_to_le16(value), addr);
474 __indirect_writew(value, addr);
478 #define iowrite16_rep(p, v, c) iowrite16_rep(p, v, c)
479 static inline void iowrite16_rep(void __iomem *addr, const void *vaddr,
482 unsigned long port = (unsigned long __force)addr;
483 if (__is_io_address(port))
484 outsw(port & PIO_MASK, vaddr, count);
486 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
487 __raw_writesw(addr, vaddr, count);
489 __indirect_writesw(addr, vaddr, count);
493 #define iowrite32(v, p) iowrite32(v, p)
494 static inline void iowrite32(u32 value, void __iomem *addr)
496 unsigned long port = (unsigned long __force)addr;
497 if (__is_io_address(port))
498 outl(value, port & PIO_MASK);
500 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
501 __raw_writel((u32 __force)cpu_to_le32(value), addr);
503 __indirect_writel(value, addr);
507 #define iowrite32_rep(p, v, c) iowrite32_rep(p, v, c)
508 static inline void iowrite32_rep(void __iomem *addr, const void *vaddr,
511 unsigned long port = (unsigned long __force)addr;
512 if (__is_io_address(port))
513 outsl(port & PIO_MASK, vaddr, count);
515 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
516 __raw_writesl(addr, vaddr, count);
518 __indirect_writesl(addr, vaddr, count);
522 #define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET))
523 #define ioport_unmap(addr)
524 #endif /* CONFIG_PCI */
526 #endif /* __ASM_ARM_ARCH_IO_H */