arch/arm/mach-ixp2000/core.c

   1 /*
   2  * arch/arm/mach-ixp2000/core.c
   3  *
   4  * Common routines used by all IXP2400/2800 based platforms.
   5  *
   6  * Author: Deepak Saxena <dsaxena@plexity.net>
   7  *
   8  * Copyright 2004 (C) MontaVista Software, Inc.
   9  *
  10  * Based on work Copyright (C) 2002-2003 Intel Corporation
  11  *
  12  * This file is licensed under the terms of the GNU General Public
  13  * License version 2. This program is licensed "as is" without any
  14  * warranty of any kind, whether express or implied.
  15  */
  16
  17 #include <linux/config.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/sched.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/serial.h>
  24 #include <linux/tty.h>
  25 #include <linux/bitops.h>
  26 #include <linux/serial_8250.h>
  27 #include <linux/mm.h>
  28
  29 #include <asm/types.h>
  30 #include <asm/setup.h>
  31 #include <asm/memory.h>
  32 #include <asm/hardware.h>
  33 #include <asm/irq.h>
  34 #include <asm/system.h>
  35 #include <asm/tlbflush.h>
  36 #include <asm/pgtable.h>
  37
  38 #include <asm/mach/map.h>
  39 #include <asm/mach/time.h>
  40 #include <asm/mach/irq.h>
  41
  42 #include <asm/arch/gpio.h>
  43
  44 static DEFINE_SPINLOCK(ixp2000_slowport_lock);
  45 static unsigned long ixp2000_slowport_irq_flags;
  46
  47 /*************************************************************************
  48  * Slowport access routines
  49  *************************************************************************/
  50 void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
  51 {
  52         spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
  53
  54         old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
  55         old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
  56         old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
  57         old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
  58         old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
  59
  60         ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
  61         ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
  62         ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
  63         ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
  64         ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
  65 }
  66
  67 void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
  68 {
  69         ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
  70         ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
  71         ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
  72         ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
  73         ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
  74
  75         spin_unlock_irqrestore(&ixp2000_slowport_lock,
  76                                         ixp2000_slowport_irq_flags);
  77 }
  78
  79 /*************************************************************************
  80  * Chip specific mappings shared by all IXP2000 systems
  81  *************************************************************************/
  82 static struct map_desc ixp2000_io_desc[] __initdata = {
  83         {
  84                 .virtual        = IXP2000_CAP_VIRT_BASE,
  85                 .pfn            = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
  86                 .length         = IXP2000_CAP_SIZE,
  87                 .type           = MT_IXP2000_DEVICE,
  88         }, {
  89                 .virtual        = IXP2000_INTCTL_VIRT_BASE,
  90                 .pfn            = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
  91                 .length         = IXP2000_INTCTL_SIZE,
  92                 .type           = MT_IXP2000_DEVICE,
  93         }, {
  94                 .virtual        = IXP2000_PCI_CREG_VIRT_BASE,
  95                 .pfn            = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
  96                 .length         = IXP2000_PCI_CREG_SIZE,
  97                 .type           = MT_IXP2000_DEVICE,
  98         }, {
  99                 .virtual        = IXP2000_PCI_CSR_VIRT_BASE,
 100                 .pfn            = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
 101                 .length         = IXP2000_PCI_CSR_SIZE,
 102                 .type           = MT_IXP2000_DEVICE,
 103         }, {
 104                 .virtual        = IXP2000_MSF_VIRT_BASE,
 105                 .pfn            = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
 106                 .length         = IXP2000_MSF_SIZE,
 107                 .type           = MT_IXP2000_DEVICE,
 108         }, {
 109                 .virtual        = IXP2000_SCRATCH_RING_VIRT_BASE,
 110                 .pfn            = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE),
 111                 .length         = IXP2000_SCRATCH_RING_SIZE,
 112                 .type           = MT_IXP2000_DEVICE,
 113         }, {
 114                 .virtual        = IXP2000_SRAM0_VIRT_BASE,
 115                 .pfn            = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE),
 116                 .length         = IXP2000_SRAM0_SIZE,
 117                 .type           = MT_IXP2000_DEVICE,
 118         }, {
 119                 .virtual        = IXP2000_PCI_IO_VIRT_BASE,
 120                 .pfn            = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
 121                 .length         = IXP2000_PCI_IO_SIZE,
 122                 .type           = MT_IXP2000_DEVICE,
 123         }, {
 124                 .virtual        = IXP2000_PCI_CFG0_VIRT_BASE,
 125                 .pfn            = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
 126                 .length         = IXP2000_PCI_CFG0_SIZE,
 127                 .type           = MT_IXP2000_DEVICE,
 128         }, {
 129                 .virtual        = IXP2000_PCI_CFG1_VIRT_BASE,
 130                 .pfn            = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
 131                 .length         = IXP2000_PCI_CFG1_SIZE,
 132                 .type           = MT_IXP2000_DEVICE,
 133         }
 134 };
 135
 136 void __init ixp2000_map_io(void)
 137 {
 138         /*
 139          * On IXP2400 CPUs we need to use MT_IXP2000_DEVICE so that
 140          * XCB=101 (to avoid triggering erratum #66), and given that
 141          * this mode speeds up I/O accesses and we have write buffer
 142          * flushes in the right places anyway, it doesn't hurt to use
 143          * XCB=101 for all IXP2000s.
 144          */
 145         iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
 146
 147         /* Set slowport to 8-bit mode.  */
 148         ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1);
 149 }
 150
 151
 152 /*************************************************************************
 153  * Serial port support for IXP2000
 154  *************************************************************************/
 155 static struct plat_serial8250_port ixp2000_serial_port[] = {
 156         {
 157                 .mapbase        = IXP2000_UART_PHYS_BASE,
 158                 .membase        = (char *)(IXP2000_UART_VIRT_BASE + 3),
 159                 .irq            = IRQ_IXP2000_UART,
 160                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 161                 .iotype         = UPIO_MEM,
 162                 .regshift       = 2,
 163                 .uartclk        = 50000000,
 164         },
 165         { },
 166 };
 167
 168 static struct resource ixp2000_uart_resource = {
 169         .start          = IXP2000_UART_PHYS_BASE,
 170         .end            = IXP2000_UART_PHYS_BASE + 0x1f,
 171         .flags          = IORESOURCE_MEM,
 172 };
 173
 174 static struct platform_device ixp2000_serial_device = {
 175         .name           = "serial8250",
 176         .id             = PLAT8250_DEV_PLATFORM,
 177         .dev            = {
 178                 .platform_data          = ixp2000_serial_port,
 179         },
 180         .num_resources  = 1,
 181         .resource       = &ixp2000_uart_resource,
 182 };
 183
 184 void __init ixp2000_uart_init(void)
 185 {
 186         platform_device_register(&ixp2000_serial_device);
 187 }
 188
 189
 190 /*************************************************************************
 191  * Timer-tick functions for IXP2000
 192  *************************************************************************/
 193 static unsigned ticks_per_jiffy;
 194 static unsigned ticks_per_usec;
 195 static unsigned next_jiffy_time;
 196 static volatile unsigned long *missing_jiffy_timer_csr;
 197
 198 unsigned long ixp2000_gettimeoffset (void)
 199 {
 200         unsigned long offset;
 201
 202         offset = next_jiffy_time - *missing_jiffy_timer_csr;
 203
 204         return offset / ticks_per_usec;
 205 }
 206
 207 static int ixp2000_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 208 {
 209         write_seqlock(&xtime_lock);
 210
 211         /* clear timer 1 */
 212         ixp2000_reg_wrb(IXP2000_T1_CLR, 1);
 213
 214         while ((signed long)(next_jiffy_time - *missing_jiffy_timer_csr)
 215                                                         >= ticks_per_jiffy) {
 216                 timer_tick(regs);
 217                 next_jiffy_time -= ticks_per_jiffy;
 218         }
 219
 220         write_sequnlock(&xtime_lock);
 221
 222         return IRQ_HANDLED;
 223 }
 224
 225 static struct irqaction ixp2000_timer_irq = {
 226         .name           = "IXP2000 Timer Tick",
 227         .flags          = SA_INTERRUPT | SA_TIMER,
 228         .handler        = ixp2000_timer_interrupt,
 229 };
 230
 231 void __init ixp2000_init_time(unsigned long tick_rate)
 232 {
 233         ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
 234         ticks_per_usec = tick_rate / 1000000;
 235
 236         /*
 237          * We use timer 1 as our timer interrupt.
 238          */
 239         ixp2000_reg_write(IXP2000_T1_CLR, 0);
 240         ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
 241         ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
 242
 243         /*
 244          * We use a second timer as a monotonic counter for tracking
 245          * missed jiffies.  The IXP2000 has four timers, but if we're
 246          * on an A-step IXP2800, timer 2 and 3 don't work, so on those
 247          * chips we use timer 4.  Timer 4 is the only timer that can
 248          * be used for the watchdog, so we use timer 2 if we're on a
 249          * non-buggy chip.
 250          */
 251         if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
 252                 printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");
 253
 254                 ixp2000_reg_write(IXP2000_T4_CLR, 0);
 255                 ixp2000_reg_write(IXP2000_T4_CLD, -1);
 256                 ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7));
 257                 missing_jiffy_timer_csr = IXP2000_T4_CSR;
 258         } else {
 259                 ixp2000_reg_write(IXP2000_T2_CLR, 0);
 260                 ixp2000_reg_write(IXP2000_T2_CLD, -1);
 261                 ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7));
 262                 missing_jiffy_timer_csr = IXP2000_T2_CSR;
 263         }
 264         next_jiffy_time = 0xffffffff;
 265
 266         /* register for interrupt */
 267         setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
 268 }
 269
 270 /*************************************************************************
 271  * GPIO helpers
 272  *************************************************************************/
 273 static unsigned long GPIO_IRQ_falling_edge;
 274 static unsigned long GPIO_IRQ_rising_edge;
 275 static unsigned long GPIO_IRQ_level_low;
 276 static unsigned long GPIO_IRQ_level_high;
 277
 278 static void update_gpio_int_csrs(void)
 279 {
 280         ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
 281         ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
 282         ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
 283         ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
 284 }
 285
 286 void gpio_line_config(int line, int direction)
 287 {
 288         unsigned long flags;
 289
 290         local_irq_save(flags);
 291         if (direction == GPIO_OUT) {
 292                 /* if it's an output, it ain't an interrupt anymore */
 293                 GPIO_IRQ_falling_edge &= ~(1 << line);
 294                 GPIO_IRQ_rising_edge &= ~(1 << line);
 295                 GPIO_IRQ_level_low &= ~(1 << line);
 296                 GPIO_IRQ_level_high &= ~(1 << line);
 297                 update_gpio_int_csrs();
 298
 299                 ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line);
 300         } else if (direction == GPIO_IN) {
 301                 ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line);
 302         }
 303         local_irq_restore(flags);
 304 }
 305
 306
 307 /*************************************************************************
 308  * IRQ handling IXP2000
 309  *************************************************************************/
 310 static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
 311 {
 312         int i;
 313         unsigned long status = *IXP2000_GPIO_INST;
 314
 315         for (i = 0; i <= 7; i++) {
 316                 if (status & (1<<i)) {
 317                         desc = irq_desc + i + IRQ_IXP2000_GPIO0;
 318                         desc_handle_irq(i + IRQ_IXP2000_GPIO0, desc, regs);
 319                 }
 320         }
 321 }
 322
 323 static int ixp2000_GPIO_irq_type(unsigned int irq, unsigned int type)
 324 {
 325         int line = irq - IRQ_IXP2000_GPIO0;
 326
 327         /*
 328          * First, configure this GPIO line as an input.
 329          */
 330         ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
 331
 332         /*
 333          * Then, set the proper trigger type.
 334          */
 335         if (type & IRQT_FALLING)
 336                 GPIO_IRQ_falling_edge |= 1 << line;
 337         else
 338                 GPIO_IRQ_falling_edge &= ~(1 << line);
 339         if (type & IRQT_RISING)
 340                 GPIO_IRQ_rising_edge |= 1 << line;
 341         else
 342                 GPIO_IRQ_rising_edge &= ~(1 << line);
 343         if (type & IRQT_LOW)
 344                 GPIO_IRQ_level_low |= 1 << line;
 345         else
 346                 GPIO_IRQ_level_low &= ~(1 << line);
 347         if (type & IRQT_HIGH)
 348                 GPIO_IRQ_level_high |= 1 << line;
 349         else
 350                 GPIO_IRQ_level_high &= ~(1 << line);
 351         update_gpio_int_csrs();
 352
 353         return 0;
 354 }
 355
 356 static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
 357 {
 358         ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 359
 360         ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 361         ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 362         ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
 363 }
 364
 365 static void ixp2000_GPIO_irq_mask(unsigned int irq)
 366 {
 367         ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 368 }
 369
 370 static void ixp2000_GPIO_irq_unmask(unsigned int irq)
 371 {
 372         ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 373 }
 374
 375 static struct irqchip ixp2000_GPIO_irq_chip = {
 376         .ack            = ixp2000_GPIO_irq_mask_ack,
 377         .mask           = ixp2000_GPIO_irq_mask,
 378         .unmask         = ixp2000_GPIO_irq_unmask,
 379         .set_type       = ixp2000_GPIO_irq_type,
 380 };
 381
 382 static void ixp2000_pci_irq_mask(unsigned int irq)
 383 {
 384         unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
 385         if (irq == IRQ_IXP2000_PCIA)
 386                 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
 387         else if (irq == IRQ_IXP2000_PCIB)
 388                 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
 389 }
 390
 391 static void ixp2000_pci_irq_unmask(unsigned int irq)
 392 {
 393         unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
 394         if (irq == IRQ_IXP2000_PCIA)
 395                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
 396         else if (irq == IRQ_IXP2000_PCIB)
 397                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
 398 }
 399
 400 /*
 401  * Error interrupts. These are used extensively by the microengine drivers
 402  */
 403 static void ixp2000_err_irq_handler(unsigned int irq, struct irqdesc *desc,  struct pt_regs *regs)
 404 {
 405         int i;
 406         unsigned long status = *IXP2000_IRQ_ERR_STATUS;
 407
 408         for(i = 31; i >= 0; i--) {
 409                 if(status & (1 << i)) {
 410                         desc = irq_desc + IRQ_IXP2000_DRAM0_MIN_ERR + i;
 411                         desc->handle(IRQ_IXP2000_DRAM0_MIN_ERR + i, desc, regs);
 412                 }
 413         }
 414 }
 415
 416 static void ixp2000_err_irq_mask(unsigned int irq)
 417 {
 418         ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
 419                         (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
 420 }
 421
 422 static void ixp2000_err_irq_unmask(unsigned int irq)
 423 {
 424         ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
 425                         (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
 426 }
 427
 428 static struct irqchip ixp2000_err_irq_chip = {
 429         .ack    = ixp2000_err_irq_mask,
 430         .mask   = ixp2000_err_irq_mask,
 431         .unmask = ixp2000_err_irq_unmask
 432 };
 433
 434 static struct irqchip ixp2000_pci_irq_chip = {
 435         .ack    = ixp2000_pci_irq_mask,
 436         .mask   = ixp2000_pci_irq_mask,
 437         .unmask = ixp2000_pci_irq_unmask
 438 };
 439
 440 static void ixp2000_irq_mask(unsigned int irq)
 441 {
 442         ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
 443 }
 444
 445 static void ixp2000_irq_unmask(unsigned int irq)
 446 {
 447         ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
 448 }
 449
 450 static struct irqchip ixp2000_irq_chip = {
 451         .ack    = ixp2000_irq_mask,
 452         .mask   = ixp2000_irq_mask,
 453         .unmask = ixp2000_irq_unmask
 454 };
 455
 456 void __init ixp2000_init_irq(void)
 457 {
 458         int irq;
 459
 460         /*
 461          * Mask all sources
 462          */
 463         ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
 464         ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
 465
 466         /* clear all GPIO edge/level detects */
 467         ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
 468         ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
 469         ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
 470         ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
 471         ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
 472
 473         /* clear PCI interrupt sources */
 474         ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
 475
 476         /*
 477          * Certain bits in the IRQ status register of the
 478          * IXP2000 are reserved. Instead of trying to map
 479          * things non 1:1 from bit position to IRQ number,
 480          * we mark the reserved IRQs as invalid. This makes
 481          * our mask/unmask code much simpler.
 482          */
 483         for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
 484                 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
 485                         set_irq_chip(irq, &ixp2000_irq_chip);
 486                         set_irq_handler(irq, do_level_IRQ);
 487                         set_irq_flags(irq, IRQF_VALID);
 488                 } else set_irq_flags(irq, 0);
 489         }
 490
 491         for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
 492                 if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
 493                                 IXP2000_VALID_ERR_IRQ_MASK) {
 494                         set_irq_chip(irq, &ixp2000_err_irq_chip);
 495                         set_irq_handler(irq, do_level_IRQ);
 496                         set_irq_flags(irq, IRQF_VALID);
 497                 }
 498                 else
 499                         set_irq_flags(irq, 0);
 500         }
 501         set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
 502
 503         for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
 504                 set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
 505                 set_irq_handler(irq, do_level_IRQ);
 506                 set_irq_flags(irq, IRQF_VALID);
 507         }
 508         set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
 509
 510         /*
 511          * Enable PCI irqs.  The actual PCI[AB] decoding is done in
 512          * entry-macro.S, so we don't need a chained handler for the
 513          * PCI interrupt source.
 514          */
 515         ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
 516         for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
 517                 set_irq_chip(irq, &ixp2000_pci_irq_chip);
 518                 set_irq_handler(irq, do_level_IRQ);
 519                 set_irq_flags(irq, IRQF_VALID);
 520         }
 521 }
 522