2 * arch/arm/mach-ixp2000/core.c
4 * Common routines used by all IXP2400/2800 based platforms.
6 * Author: Deepak Saxena <dsaxena@plexity.net>
8 * Copyright 2004 (C) MontaVista Software, Inc.
10 * Based on work Copyright (C) 2002-2003 Intel Corporation
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/spinlock.h>
20 #include <linux/sched.h>
21 #include <linux/interrupt.h>
22 #include <linux/serial.h>
23 #include <linux/tty.h>
24 #include <linux/bitops.h>
25 #include <linux/serial_8250.h>
28 #include <asm/types.h>
29 #include <asm/setup.h>
30 #include <asm/memory.h>
31 #include <asm/hardware.h>
33 #include <asm/system.h>
34 #include <asm/tlbflush.h>
35 #include <asm/pgtable.h>
37 #include <asm/mach/map.h>
38 #include <asm/mach/time.h>
39 #include <asm/mach/irq.h>
41 #include <asm/arch/gpio.h>
43 static DEFINE_SPINLOCK(ixp2000_slowport_lock);
44 static unsigned long ixp2000_slowport_irq_flags;
46 /*************************************************************************
47 * Slowport access routines
48 *************************************************************************/
49 void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
51 spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
53 old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
54 old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
55 old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
56 old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
57 old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
59 ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
60 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
61 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
62 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
63 ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
66 void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
68 ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
69 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
70 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
71 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
72 ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
74 spin_unlock_irqrestore(&ixp2000_slowport_lock,
75 ixp2000_slowport_irq_flags);
78 /*************************************************************************
79 * Chip specific mappings shared by all IXP2000 systems
80 *************************************************************************/
81 static struct map_desc ixp2000_io_desc[] __initdata = {
83 .virtual = IXP2000_CAP_VIRT_BASE,
84 .pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
85 .length = IXP2000_CAP_SIZE,
86 .type = MT_IXP2000_DEVICE,
88 .virtual = IXP2000_INTCTL_VIRT_BASE,
89 .pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
90 .length = IXP2000_INTCTL_SIZE,
91 .type = MT_IXP2000_DEVICE,
93 .virtual = IXP2000_PCI_CREG_VIRT_BASE,
94 .pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
95 .length = IXP2000_PCI_CREG_SIZE,
96 .type = MT_IXP2000_DEVICE,
98 .virtual = IXP2000_PCI_CSR_VIRT_BASE,
99 .pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
100 .length = IXP2000_PCI_CSR_SIZE,
101 .type = MT_IXP2000_DEVICE,
103 .virtual = IXP2000_MSF_VIRT_BASE,
104 .pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
105 .length = IXP2000_MSF_SIZE,
106 .type = MT_IXP2000_DEVICE,
108 .virtual = IXP2000_SCRATCH_RING_VIRT_BASE,
109 .pfn = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE),
110 .length = IXP2000_SCRATCH_RING_SIZE,
111 .type = MT_IXP2000_DEVICE,
113 .virtual = IXP2000_SRAM0_VIRT_BASE,
114 .pfn = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE),
115 .length = IXP2000_SRAM0_SIZE,
116 .type = MT_IXP2000_DEVICE,
118 .virtual = IXP2000_PCI_IO_VIRT_BASE,
119 .pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
120 .length = IXP2000_PCI_IO_SIZE,
121 .type = MT_IXP2000_DEVICE,
123 .virtual = IXP2000_PCI_CFG0_VIRT_BASE,
124 .pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
125 .length = IXP2000_PCI_CFG0_SIZE,
126 .type = MT_IXP2000_DEVICE,
128 .virtual = IXP2000_PCI_CFG1_VIRT_BASE,
129 .pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
130 .length = IXP2000_PCI_CFG1_SIZE,
131 .type = MT_IXP2000_DEVICE,
135 void __init ixp2000_map_io(void)
138 * On IXP2400 CPUs we need to use MT_IXP2000_DEVICE so that
139 * XCB=101 (to avoid triggering erratum #66), and given that
140 * this mode speeds up I/O accesses and we have write buffer
141 * flushes in the right places anyway, it doesn't hurt to use
142 * XCB=101 for all IXP2000s.
144 iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
146 /* Set slowport to 8-bit mode. */
147 ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1);
151 /*************************************************************************
152 * Serial port support for IXP2000
153 *************************************************************************/
154 static struct plat_serial8250_port ixp2000_serial_port[] = {
156 .mapbase = IXP2000_UART_PHYS_BASE,
157 .membase = (char *)(IXP2000_UART_VIRT_BASE + 3),
158 .irq = IRQ_IXP2000_UART,
159 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
167 static struct resource ixp2000_uart_resource = {
168 .start = IXP2000_UART_PHYS_BASE,
169 .end = IXP2000_UART_PHYS_BASE + 0x1f,
170 .flags = IORESOURCE_MEM,
173 static struct platform_device ixp2000_serial_device = {
174 .name = "serial8250",
175 .id = PLAT8250_DEV_PLATFORM,
177 .platform_data = ixp2000_serial_port,
180 .resource = &ixp2000_uart_resource,
183 void __init ixp2000_uart_init(void)
185 platform_device_register(&ixp2000_serial_device);
189 /*************************************************************************
190 * Timer-tick functions for IXP2000
191 *************************************************************************/
192 static unsigned ticks_per_jiffy;
193 static unsigned ticks_per_usec;
194 static unsigned next_jiffy_time;
195 static volatile unsigned long *missing_jiffy_timer_csr;
197 unsigned long ixp2000_gettimeoffset (void)
199 unsigned long offset;
201 offset = next_jiffy_time - *missing_jiffy_timer_csr;
203 return offset / ticks_per_usec;
206 static int ixp2000_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
208 write_seqlock(&xtime_lock);
211 ixp2000_reg_wrb(IXP2000_T1_CLR, 1);
213 while ((signed long)(next_jiffy_time - *missing_jiffy_timer_csr)
214 >= ticks_per_jiffy) {
216 next_jiffy_time -= ticks_per_jiffy;
219 write_sequnlock(&xtime_lock);
224 static struct irqaction ixp2000_timer_irq = {
225 .name = "IXP2000 Timer Tick",
226 .flags = SA_INTERRUPT | SA_TIMER,
227 .handler = ixp2000_timer_interrupt,
230 void __init ixp2000_init_time(unsigned long tick_rate)
232 ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
233 ticks_per_usec = tick_rate / 1000000;
236 * We use timer 1 as our timer interrupt.
238 ixp2000_reg_write(IXP2000_T1_CLR, 0);
239 ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
240 ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
243 * We use a second timer as a monotonic counter for tracking
244 * missed jiffies. The IXP2000 has four timers, but if we're
245 * on an A-step IXP2800, timer 2 and 3 don't work, so on those
246 * chips we use timer 4. Timer 4 is the only timer that can
247 * be used for the watchdog, so we use timer 2 if we're on a
250 if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
251 printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");
253 ixp2000_reg_write(IXP2000_T4_CLR, 0);
254 ixp2000_reg_write(IXP2000_T4_CLD, -1);
255 ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7));
256 missing_jiffy_timer_csr = IXP2000_T4_CSR;
258 ixp2000_reg_write(IXP2000_T2_CLR, 0);
259 ixp2000_reg_write(IXP2000_T2_CLD, -1);
260 ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7));
261 missing_jiffy_timer_csr = IXP2000_T2_CSR;
263 next_jiffy_time = 0xffffffff;
265 /* register for interrupt */
266 setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
269 /*************************************************************************
271 *************************************************************************/
272 static unsigned long GPIO_IRQ_falling_edge;
273 static unsigned long GPIO_IRQ_rising_edge;
274 static unsigned long GPIO_IRQ_level_low;
275 static unsigned long GPIO_IRQ_level_high;
277 static void update_gpio_int_csrs(void)
279 ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
280 ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
281 ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
282 ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
285 void gpio_line_config(int line, int direction)
289 local_irq_save(flags);
290 if (direction == GPIO_OUT) {
291 /* if it's an output, it ain't an interrupt anymore */
292 GPIO_IRQ_falling_edge &= ~(1 << line);
293 GPIO_IRQ_rising_edge &= ~(1 << line);
294 GPIO_IRQ_level_low &= ~(1 << line);
295 GPIO_IRQ_level_high &= ~(1 << line);
296 update_gpio_int_csrs();
298 ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line);
299 } else if (direction == GPIO_IN) {
300 ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line);
302 local_irq_restore(flags);
304 EXPORT_SYMBOL(gpio_line_config);
307 /*************************************************************************
308 * IRQ handling IXP2000
309 *************************************************************************/
310 static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
313 unsigned long status = *IXP2000_GPIO_INST;
315 for (i = 0; i <= 7; i++) {
316 if (status & (1<<i)) {
317 desc = irq_desc + i + IRQ_IXP2000_GPIO0;
318 desc_handle_irq(i + IRQ_IXP2000_GPIO0, desc, regs);
323 static int ixp2000_GPIO_irq_type(unsigned int irq, unsigned int type)
325 int line = irq - IRQ_IXP2000_GPIO0;
328 * First, configure this GPIO line as an input.
330 ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
333 * Then, set the proper trigger type.
335 if (type & IRQT_FALLING)
336 GPIO_IRQ_falling_edge |= 1 << line;
338 GPIO_IRQ_falling_edge &= ~(1 << line);
339 if (type & IRQT_RISING)
340 GPIO_IRQ_rising_edge |= 1 << line;
342 GPIO_IRQ_rising_edge &= ~(1 << line);
344 GPIO_IRQ_level_low |= 1 << line;
346 GPIO_IRQ_level_low &= ~(1 << line);
347 if (type & IRQT_HIGH)
348 GPIO_IRQ_level_high |= 1 << line;
350 GPIO_IRQ_level_high &= ~(1 << line);
351 update_gpio_int_csrs();
356 static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
358 ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
360 ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
361 ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
362 ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
365 static void ixp2000_GPIO_irq_mask(unsigned int irq)
367 ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
370 static void ixp2000_GPIO_irq_unmask(unsigned int irq)
372 ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
375 static struct irqchip ixp2000_GPIO_irq_chip = {
376 .ack = ixp2000_GPIO_irq_mask_ack,
377 .mask = ixp2000_GPIO_irq_mask,
378 .unmask = ixp2000_GPIO_irq_unmask,
379 .set_type = ixp2000_GPIO_irq_type,
382 static void ixp2000_pci_irq_mask(unsigned int irq)
384 unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
385 if (irq == IRQ_IXP2000_PCIA)
386 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
387 else if (irq == IRQ_IXP2000_PCIB)
388 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
391 static void ixp2000_pci_irq_unmask(unsigned int irq)
393 unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
394 if (irq == IRQ_IXP2000_PCIA)
395 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
396 else if (irq == IRQ_IXP2000_PCIB)
397 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
401 * Error interrupts. These are used extensively by the microengine drivers
403 static void ixp2000_err_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
406 unsigned long status = *IXP2000_IRQ_ERR_STATUS;
408 for(i = 31; i >= 0; i--) {
409 if(status & (1 << i)) {
410 desc = irq_desc + IRQ_IXP2000_DRAM0_MIN_ERR + i;
411 desc->handle(IRQ_IXP2000_DRAM0_MIN_ERR + i, desc, regs);
416 static void ixp2000_err_irq_mask(unsigned int irq)
418 ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
419 (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
422 static void ixp2000_err_irq_unmask(unsigned int irq)
424 ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
425 (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
428 static struct irqchip ixp2000_err_irq_chip = {
429 .ack = ixp2000_err_irq_mask,
430 .mask = ixp2000_err_irq_mask,
431 .unmask = ixp2000_err_irq_unmask
434 static struct irqchip ixp2000_pci_irq_chip = {
435 .ack = ixp2000_pci_irq_mask,
436 .mask = ixp2000_pci_irq_mask,
437 .unmask = ixp2000_pci_irq_unmask
440 static void ixp2000_irq_mask(unsigned int irq)
442 ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
445 static void ixp2000_irq_unmask(unsigned int irq)
447 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
450 static struct irqchip ixp2000_irq_chip = {
451 .ack = ixp2000_irq_mask,
452 .mask = ixp2000_irq_mask,
453 .unmask = ixp2000_irq_unmask
456 void __init ixp2000_init_irq(void)
463 ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
464 ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
466 /* clear all GPIO edge/level detects */
467 ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
468 ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
469 ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
470 ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
471 ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
473 /* clear PCI interrupt sources */
474 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
477 * Certain bits in the IRQ status register of the
478 * IXP2000 are reserved. Instead of trying to map
479 * things non 1:1 from bit position to IRQ number,
480 * we mark the reserved IRQs as invalid. This makes
481 * our mask/unmask code much simpler.
483 for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
484 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
485 set_irq_chip(irq, &ixp2000_irq_chip);
486 set_irq_handler(irq, do_level_IRQ);
487 set_irq_flags(irq, IRQF_VALID);
488 } else set_irq_flags(irq, 0);
491 for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
492 if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
493 IXP2000_VALID_ERR_IRQ_MASK) {
494 set_irq_chip(irq, &ixp2000_err_irq_chip);
495 set_irq_handler(irq, do_level_IRQ);
496 set_irq_flags(irq, IRQF_VALID);
499 set_irq_flags(irq, 0);
501 set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
503 for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
504 set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
505 set_irq_handler(irq, do_level_IRQ);
506 set_irq_flags(irq, IRQF_VALID);
508 set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
511 * Enable PCI irqs. The actual PCI[AB] decoding is done in
512 * entry-macro.S, so we don't need a chained handler for the
513 * PCI interrupt source.
515 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
516 for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
517 set_irq_chip(irq, &ixp2000_pci_irq_chip);
518 set_irq_handler(irq, do_level_IRQ);
519 set_irq_flags(irq, IRQF_VALID);