Merge remote branch 'nouveau/for-airlied' into drm-linus
[pandora-kernel.git] / arch / arm / mach-iop13xx / tpmi.c
1 /*
2  * iop13xx tpmi device resources
3  * Copyright (c) 2005-2006, Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16  * Place - Suite 330, Boston, MA 02111-1307 USA.
17  *
18  */
19
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/io.h>
25 #include <asm/irq.h>
26 #include <asm/sizes.h>
27
28 /* assumes CONTROLLER_ONLY# is never asserted in the ESSR register */
29 #define IOP13XX_TPMI_MMR(dev)   IOP13XX_REG_ADDR32_PHYS(0x48000 + (dev << 12))
30 #define IOP13XX_TPMI_MEM(dev)   IOP13XX_REG_ADDR32_PHYS(0x60000 + (dev << 13))
31 #define IOP13XX_TPMI_CTRL(dev)  IOP13XX_REG_ADDR32_PHYS(0x50000 + (dev << 10))
32 #define IOP13XX_TPMI_IOP_CTRL(dev) (IOP13XX_TPMI_CTRL(dev) + 0x2000)
33 #define IOP13XX_TPMI_MMR_SIZE       (SZ_4K - 1)
34 #define IOP13XX_TPMI_MEM_SIZE       (255)
35 #define IOP13XX_TPMI_MEM_CTRL       (SZ_1K - 1)
36 #define IOP13XX_TPMI_RESOURCE_MMR  0
37 #define IOP13XX_TPMI_RESOURCE_MEM  1
38 #define IOP13XX_TPMI_RESOURCE_CTRL 2
39 #define IOP13XX_TPMI_RESOURCE_IOP_CTRL 3
40 #define IOP13XX_TPMI_RESOURCE_IRQ  4
41
42 static struct resource iop13xx_tpmi_0_resources[] = {
43         [IOP13XX_TPMI_RESOURCE_MMR] = {
44                 .start = IOP13XX_TPMI_MMR(4), /* tpmi0 starts at dev == 4 */
45                 .end = IOP13XX_TPMI_MMR(4) + IOP13XX_TPMI_MMR_SIZE,
46                 .flags = IORESOURCE_MEM,
47         },
48         [IOP13XX_TPMI_RESOURCE_MEM] = {
49                 .start = IOP13XX_TPMI_MEM(0),
50                 .end = IOP13XX_TPMI_MEM(0) + IOP13XX_TPMI_MEM_SIZE,
51                 .flags = IORESOURCE_MEM,
52         },
53         [IOP13XX_TPMI_RESOURCE_CTRL] = {
54                 .start = IOP13XX_TPMI_CTRL(0),
55                 .end = IOP13XX_TPMI_CTRL(0) + IOP13XX_TPMI_MEM_CTRL,
56                 .flags = IORESOURCE_MEM,
57         },
58         [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
59                 .start = IOP13XX_TPMI_IOP_CTRL(0),
60                 .end = IOP13XX_TPMI_IOP_CTRL(0) + IOP13XX_TPMI_MEM_CTRL,
61                 .flags = IORESOURCE_MEM,
62         },
63         [IOP13XX_TPMI_RESOURCE_IRQ] = {
64                 .start = IRQ_IOP13XX_TPMI0_OUT,
65                 .end = IRQ_IOP13XX_TPMI0_OUT,
66                 .flags = IORESOURCE_IRQ
67         }
68 };
69
70 static struct resource iop13xx_tpmi_1_resources[] = {
71         [IOP13XX_TPMI_RESOURCE_MMR] = {
72                 .start = IOP13XX_TPMI_MMR(1),
73                 .end = IOP13XX_TPMI_MMR(1) + IOP13XX_TPMI_MMR_SIZE,
74                 .flags = IORESOURCE_MEM,
75         },
76         [IOP13XX_TPMI_RESOURCE_MEM] = {
77                 .start = IOP13XX_TPMI_MEM(1),
78                 .end = IOP13XX_TPMI_MEM(1) + IOP13XX_TPMI_MEM_SIZE,
79                 .flags = IORESOURCE_MEM,
80         },
81         [IOP13XX_TPMI_RESOURCE_CTRL] = {
82                 .start = IOP13XX_TPMI_CTRL(1),
83                 .end = IOP13XX_TPMI_CTRL(1) + IOP13XX_TPMI_MEM_CTRL,
84                 .flags = IORESOURCE_MEM,
85         },
86         [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
87                 .start = IOP13XX_TPMI_IOP_CTRL(1),
88                 .end = IOP13XX_TPMI_IOP_CTRL(1) + IOP13XX_TPMI_MEM_CTRL,
89                 .flags = IORESOURCE_MEM,
90         },
91         [IOP13XX_TPMI_RESOURCE_IRQ] = {
92                 .start = IRQ_IOP13XX_TPMI1_OUT,
93                 .end = IRQ_IOP13XX_TPMI1_OUT,
94                 .flags = IORESOURCE_IRQ
95         }
96 };
97
98 static struct resource iop13xx_tpmi_2_resources[] = {
99         [IOP13XX_TPMI_RESOURCE_MMR] = {
100                 .start = IOP13XX_TPMI_MMR(2),
101                 .end = IOP13XX_TPMI_MMR(2) + IOP13XX_TPMI_MMR_SIZE,
102                 .flags = IORESOURCE_MEM,
103         },
104         [IOP13XX_TPMI_RESOURCE_MEM] = {
105                 .start = IOP13XX_TPMI_MEM(2),
106                 .end = IOP13XX_TPMI_MEM(2) + IOP13XX_TPMI_MEM_SIZE,
107                 .flags = IORESOURCE_MEM,
108         },
109         [IOP13XX_TPMI_RESOURCE_CTRL] = {
110                 .start = IOP13XX_TPMI_CTRL(2),
111                 .end = IOP13XX_TPMI_CTRL(2) + IOP13XX_TPMI_MEM_CTRL,
112                 .flags = IORESOURCE_MEM,
113         },
114         [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
115                 .start = IOP13XX_TPMI_IOP_CTRL(2),
116                 .end = IOP13XX_TPMI_IOP_CTRL(2) + IOP13XX_TPMI_MEM_CTRL,
117                 .flags = IORESOURCE_MEM,
118         },
119         [IOP13XX_TPMI_RESOURCE_IRQ] = {
120                 .start = IRQ_IOP13XX_TPMI2_OUT,
121                 .end = IRQ_IOP13XX_TPMI2_OUT,
122                 .flags = IORESOURCE_IRQ
123         }
124 };
125
126 static struct resource iop13xx_tpmi_3_resources[] = {
127         [IOP13XX_TPMI_RESOURCE_MMR] = {
128                 .start = IOP13XX_TPMI_MMR(3),
129                 .end = IOP13XX_TPMI_MMR(3) + IOP13XX_TPMI_MMR_SIZE,
130                 .flags = IORESOURCE_MEM,
131         },
132         [IOP13XX_TPMI_RESOURCE_MEM] = {
133                 .start = IOP13XX_TPMI_MEM(3),
134                 .end = IOP13XX_TPMI_MEM(3) + IOP13XX_TPMI_MEM_SIZE,
135                 .flags = IORESOURCE_MEM,
136         },
137         [IOP13XX_TPMI_RESOURCE_CTRL] = {
138                 .start = IOP13XX_TPMI_CTRL(3),
139                 .end = IOP13XX_TPMI_CTRL(3) + IOP13XX_TPMI_MEM_CTRL,
140                 .flags = IORESOURCE_MEM,
141         },
142         [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
143                 .start = IOP13XX_TPMI_IOP_CTRL(3),
144                 .end = IOP13XX_TPMI_IOP_CTRL(3) + IOP13XX_TPMI_MEM_CTRL,
145                 .flags = IORESOURCE_MEM,
146         },
147         [IOP13XX_TPMI_RESOURCE_IRQ] = {
148                 .start = IRQ_IOP13XX_TPMI3_OUT,
149                 .end = IRQ_IOP13XX_TPMI3_OUT,
150                 .flags = IORESOURCE_IRQ
151         }
152 };
153
154 u64 iop13xx_tpmi_mask = DMA_BIT_MASK(64);
155 static struct platform_device iop13xx_tpmi_0_device = {
156         .name = "iop-tpmi",
157         .id = 0,
158         .num_resources = ARRAY_SIZE(iop13xx_tpmi_0_resources),
159         .resource = iop13xx_tpmi_0_resources,
160         .dev = {
161                 .dma_mask          = &iop13xx_tpmi_mask,
162                 .coherent_dma_mask = DMA_BIT_MASK(64),
163         },
164 };
165
166 static struct platform_device iop13xx_tpmi_1_device = {
167         .name = "iop-tpmi",
168         .id = 1,
169         .num_resources = ARRAY_SIZE(iop13xx_tpmi_1_resources),
170         .resource = iop13xx_tpmi_1_resources,
171         .dev = {
172                 .dma_mask          = &iop13xx_tpmi_mask,
173                 .coherent_dma_mask = DMA_BIT_MASK(64),
174         },
175 };
176
177 static struct platform_device iop13xx_tpmi_2_device = {
178         .name = "iop-tpmi",
179         .id = 2,
180         .num_resources = ARRAY_SIZE(iop13xx_tpmi_2_resources),
181         .resource = iop13xx_tpmi_2_resources,
182         .dev = {
183                 .dma_mask          = &iop13xx_tpmi_mask,
184                 .coherent_dma_mask = DMA_BIT_MASK(64),
185         },
186 };
187
188 static struct platform_device iop13xx_tpmi_3_device = {
189         .name = "iop-tpmi",
190         .id = 3,
191         .num_resources = ARRAY_SIZE(iop13xx_tpmi_3_resources),
192         .resource = iop13xx_tpmi_3_resources,
193         .dev = {
194                 .dma_mask          = &iop13xx_tpmi_mask,
195                 .coherent_dma_mask = DMA_BIT_MASK(64),
196         },
197 };
198
199 __init void iop13xx_add_tpmi_devices(void)
200 {
201         unsigned short device_id;
202
203         /* tpmi's not present on iop341 or iop342 */
204         if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
205                 /* ATUE must be present */
206                 device_id = __raw_readw(IOP13XX_ATUE_DID);
207         else
208                 /* ATUX must be present */
209                 device_id = __raw_readw(IOP13XX_ATUX_DID);
210
211         switch (device_id) {
212         /* iop34[1|2] 0-tpmi */
213         case 0x3380:
214         case 0x3384:
215         case 0x3388:
216         case 0x338c:
217         case 0x3382:
218         case 0x3386:
219         case 0x338a:
220         case 0x338e:
221                 return;
222         /* iop348 1-tpmi */
223         case 0x3310:
224         case 0x3312:
225         case 0x3314:
226         case 0x3318:
227         case 0x331a:
228         case 0x331c:
229         case 0x33c0:
230         case 0x33c2:
231         case 0x33c4:
232         case 0x33c8:
233         case 0x33ca:
234         case 0x33cc:
235         case 0x33b0:
236         case 0x33b2:
237         case 0x33b4:
238         case 0x33b8:
239         case 0x33ba:
240         case 0x33bc:
241         case 0x3320:
242         case 0x3322:
243         case 0x3324:
244         case 0x3328:
245         case 0x332a:
246         case 0x332c:
247                 platform_device_register(&iop13xx_tpmi_0_device);
248                 return;
249         default:
250                 platform_device_register(&iop13xx_tpmi_0_device);
251                 platform_device_register(&iop13xx_tpmi_1_device);
252                 platform_device_register(&iop13xx_tpmi_2_device);
253                 platform_device_register(&iop13xx_tpmi_3_device);
254                 return;
255         }
256 }