2 * linux/arch/arm/mach-integrator/integrator_cp.c
4 * Copyright (C) 2003 Deep Blue Solutions Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/list.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/slab.h>
17 #include <linux/string.h>
18 #include <linux/sysdev.h>
19 #include <linux/amba/bus.h>
20 #include <linux/amba/kmi.h>
21 #include <linux/amba/clcd.h>
22 #include <linux/amba/mmci.h>
25 #include <asm/clkdev.h>
26 #include <mach/clkdev.h>
27 #include <mach/hardware.h>
28 #include <mach/platform.h>
30 #include <asm/setup.h>
31 #include <asm/mach-types.h>
32 #include <asm/hardware/icst525.h>
37 #include <asm/mach/arch.h>
38 #include <asm/mach/flash.h>
39 #include <asm/mach/irq.h>
40 #include <asm/mach/map.h>
41 #include <asm/mach/time.h>
45 #define INTCP_PA_FLASH_BASE 0x24000000
46 #define INTCP_FLASH_SIZE SZ_32M
48 #define INTCP_PA_CLCD_BASE 0xc0000000
50 #define INTCP_VA_CIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE + 0x40)
51 #define INTCP_VA_PIC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE)
52 #define INTCP_VA_SIC_BASE IO_ADDRESS(INTEGRATOR_CP_SIC_BASE)
54 #define INTCP_ETH_SIZE 0x10
56 #define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
57 #define INTCP_FLASHPROG 0x04
58 #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
59 #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
63 * f1000000 10000000 Core module registers
64 * f1100000 11000000 System controller registers
65 * f1200000 12000000 EBI registers
66 * f1300000 13000000 Counter/Timer
67 * f1400000 14000000 Interrupt controller
68 * f1600000 16000000 UART 0
69 * f1700000 17000000 UART 1
70 * f1a00000 1a000000 Debug LEDs
71 * fc900000 c9000000 GPIO
72 * fca00000 ca000000 SIC
73 * fcb00000 cb000000 CP system control
76 static struct map_desc intcp_io_desc[] __initdata = {
78 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
79 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
83 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
84 .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
88 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
89 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
93 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
94 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
98 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
99 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
103 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
104 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
108 .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
109 .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
113 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
114 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
118 .virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
119 .pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
123 .virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
124 .pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
128 .virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
129 .pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
135 static void __init intcp_map_io(void)
137 iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
140 #define cic_writel __raw_writel
141 #define cic_readl __raw_readl
142 #define pic_writel __raw_writel
143 #define pic_readl __raw_readl
144 #define sic_writel __raw_writel
145 #define sic_readl __raw_readl
147 static void cic_mask_irq(unsigned int irq)
149 irq -= IRQ_CIC_START;
150 cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
153 static void cic_unmask_irq(unsigned int irq)
155 irq -= IRQ_CIC_START;
156 cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
159 static struct irq_chip cic_chip = {
162 .mask = cic_mask_irq,
163 .unmask = cic_unmask_irq,
166 static void pic_mask_irq(unsigned int irq)
168 irq -= IRQ_PIC_START;
169 pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
172 static void pic_unmask_irq(unsigned int irq)
174 irq -= IRQ_PIC_START;
175 pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
178 static struct irq_chip pic_chip = {
181 .mask = pic_mask_irq,
182 .unmask = pic_unmask_irq,
185 static void sic_mask_irq(unsigned int irq)
187 irq -= IRQ_SIC_START;
188 sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
191 static void sic_unmask_irq(unsigned int irq)
193 irq -= IRQ_SIC_START;
194 sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
197 static struct irq_chip sic_chip = {
200 .mask = sic_mask_irq,
201 .unmask = sic_unmask_irq,
205 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
207 unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
210 do_bad_IRQ(irq, desc);
215 irq = ffs(status) - 1;
216 status &= ~(1 << irq);
218 irq += IRQ_SIC_START;
220 generic_handle_irq(irq);
224 static void __init intcp_init_irq(void)
229 * Disable all interrupt sources
231 pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
232 pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
234 for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
239 set_irq_chip(i, &pic_chip);
240 set_irq_handler(i, handle_level_irq);
241 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
244 cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
245 cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
247 for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
248 set_irq_chip(i, &cic_chip);
249 set_irq_handler(i, handle_level_irq);
250 set_irq_flags(i, IRQF_VALID);
253 sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
254 sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
256 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
257 set_irq_chip(i, &sic_chip);
258 set_irq_handler(i, handle_level_irq);
259 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
262 set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
268 #define CM_LOCK IO_ADDRESS(INTEGRATOR_HDR_LOCK)
269 #define CM_AUXOSC IO_ADDRESS(INTEGRATOR_HDR_BASE + 0x1c)
271 static const struct icst_params cp_auxvco_params = {
273 .vco_max = ICST525_VCO_MAX_5V,
280 static void cp_auxvco_set(struct clk *clk, struct icst_vco vco)
284 val = readl(CM_AUXOSC) & ~0x7ffff;
285 val |= vco.v | (vco.r << 9) | (vco.s << 16);
287 writel(0xa05f, CM_LOCK);
288 writel(val, CM_AUXOSC);
292 static struct clk cp_auxclk = {
293 .params = &cp_auxvco_params,
294 .setvco = cp_auxvco_set,
297 static struct clk_lookup cp_lookups[] = {
307 static int intcp_flash_init(void)
311 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
312 val |= CINTEGRATOR_FLASHPROG_FLWREN;
313 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
318 static void intcp_flash_exit(void)
322 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
323 val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
324 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
327 static void intcp_flash_set_vpp(int on)
331 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
333 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
335 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
336 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
339 static struct flash_platform_data intcp_flash_data = {
340 .map_name = "cfi_probe",
342 .init = intcp_flash_init,
343 .exit = intcp_flash_exit,
344 .set_vpp = intcp_flash_set_vpp,
347 static struct resource intcp_flash_resource = {
348 .start = INTCP_PA_FLASH_BASE,
349 .end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
350 .flags = IORESOURCE_MEM,
353 static struct platform_device intcp_flash_device = {
357 .platform_data = &intcp_flash_data,
360 .resource = &intcp_flash_resource,
363 static struct resource smc91x_resources[] = {
365 .start = INTEGRATOR_CP_ETH_BASE,
366 .end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
367 .flags = IORESOURCE_MEM,
370 .start = IRQ_CP_ETHINT,
371 .end = IRQ_CP_ETHINT,
372 .flags = IORESOURCE_IRQ,
376 static struct platform_device smc91x_device = {
379 .num_resources = ARRAY_SIZE(smc91x_resources),
380 .resource = smc91x_resources,
383 static struct platform_device *intcp_devs[] __initdata = {
389 * It seems that the card insertion interrupt remains active after
390 * we've acknowledged it. We therefore ignore the interrupt, and
391 * rely on reading it from the SIC. This also means that we must
392 * clear the latched interrupt.
394 static unsigned int mmc_status(struct device *dev)
396 unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
397 writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));
402 static struct mmci_platform_data mmc_data = {
403 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
404 .status = mmc_status,
409 static struct amba_device mmc_device = {
411 .init_name = "mb:1c",
412 .platform_data = &mmc_data,
415 .start = INTEGRATOR_CP_MMC_BASE,
416 .end = INTEGRATOR_CP_MMC_BASE + SZ_4K - 1,
417 .flags = IORESOURCE_MEM,
419 .irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
423 static struct amba_device aaci_device = {
425 .init_name = "mb:1d",
428 .start = INTEGRATOR_CP_AACI_BASE,
429 .end = INTEGRATOR_CP_AACI_BASE + SZ_4K - 1,
430 .flags = IORESOURCE_MEM,
432 .irq = { IRQ_CP_AACIINT, NO_IRQ },
440 static struct clcd_panel vga = {
454 .vmode = FB_VMODE_NONINTERLACED,
458 .tim2 = TIM2_BCD | TIM2_IPC,
459 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
465 * Ensure VGA is selected.
467 static void cp_clcd_enable(struct clcd_fb *fb)
471 if (fb->fb.var.bits_per_pixel <= 8)
472 val = CM_CTRL_LCDMUXSEL_VGA_8421BPP;
473 else if (fb->fb.var.bits_per_pixel <= 16)
474 val = CM_CTRL_LCDMUXSEL_VGA_16BPP
475 | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1
476 | CM_CTRL_STATIC1 | CM_CTRL_STATIC2;
478 val = 0; /* no idea for this, don't trust the docs */
480 cm_control(CM_CTRL_LCDMUXSEL_MASK|
486 CM_CTRL_n24BITEN, val);
489 static unsigned long framesize = SZ_1M;
491 static int cp_clcd_setup(struct clcd_fb *fb)
497 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
499 if (!fb->fb.screen_base) {
500 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
504 fb->fb.fix.smem_start = dma;
505 fb->fb.fix.smem_len = framesize;
510 static int cp_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
512 return dma_mmap_writecombine(&fb->dev->dev, vma,
514 fb->fb.fix.smem_start,
515 fb->fb.fix.smem_len);
518 static void cp_clcd_remove(struct clcd_fb *fb)
520 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
521 fb->fb.screen_base, fb->fb.fix.smem_start);
524 static struct clcd_board clcd_data = {
525 .name = "Integrator/CP",
526 .check = clcdfb_check,
527 .decode = clcdfb_decode,
528 .enable = cp_clcd_enable,
529 .setup = cp_clcd_setup,
530 .mmap = cp_clcd_mmap,
531 .remove = cp_clcd_remove,
534 static struct amba_device clcd_device = {
536 .init_name = "mb:c0",
537 .coherent_dma_mask = ~0,
538 .platform_data = &clcd_data,
541 .start = INTCP_PA_CLCD_BASE,
542 .end = INTCP_PA_CLCD_BASE + SZ_4K - 1,
543 .flags = IORESOURCE_MEM,
546 .irq = { IRQ_CP_CLCDCINT, NO_IRQ },
550 static struct amba_device *amba_devs[] __initdata = {
556 static void __init intcp_init(void)
560 clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));
561 platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
563 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
564 struct amba_device *d = amba_devs[i];
565 amba_device_register(d, &iomem_resource);
569 #define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable */
571 static void __init intcp_timer_init(void)
573 integrator_time_init(1000, TIMER_CTRL_IE);
576 static struct sys_timer cp_timer = {
577 .init = intcp_timer_init,
580 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
581 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
582 .phys_io = 0x16000000,
583 .io_pg_offst = ((0xf1600000) >> 18) & 0xfffc,
584 .boot_params = 0x00000100,
585 .map_io = intcp_map_io,
586 .init_irq = intcp_init_irq,
588 .init_machine = intcp_init,