2 * linux/arch/arm/mach-integrator/integrator_ap.c
4 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/string.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/amba/bus.h>
29 #include <linux/amba/kmi.h>
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/interrupt.h>
35 #include <mach/hardware.h>
36 #include <mach/platform.h>
37 #include <asm/hardware/arm_timer.h>
39 #include <asm/setup.h>
40 #include <asm/param.h> /* HZ */
41 #include <asm/mach-types.h>
45 #include <asm/mach/arch.h>
46 #include <asm/mach/flash.h>
47 #include <asm/mach/irq.h>
48 #include <asm/mach/map.h>
49 #include <asm/mach/time.h>
51 #include <plat/fpga-irq.h>
56 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
59 * Setup a VA for the Integrator interrupt controller (for header #0,
62 #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
63 #define VA_SC_BASE __io_address(INTEGRATOR_SC_BASE)
64 #define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE)
65 #define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC)
69 * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
70 * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
71 * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
72 * ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
73 * ef000000 Cache flush
74 * f1000000 10000000 Core module registers
75 * f1100000 11000000 System controller registers
76 * f1200000 12000000 EBI registers
77 * f1300000 13000000 Counter/Timer
78 * f1400000 14000000 Interrupt controller
79 * f1600000 16000000 UART 0
80 * f1700000 17000000 UART 1
81 * f1a00000 1a000000 Debug LEDs
82 * f1b00000 1b000000 GPIO
85 static struct map_desc ap_io_desc[] __initdata = {
87 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
88 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
92 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
93 .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
97 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
98 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
102 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
103 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
107 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
108 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
112 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
113 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
117 .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
118 .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
122 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
123 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
127 .virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
128 .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
132 .virtual = PCI_MEMORY_VADDR,
133 .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
137 .virtual = PCI_CONFIG_VADDR,
138 .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
142 .virtual = PCI_V3_VADDR,
143 .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE),
147 .virtual = PCI_IO_VADDR,
148 .pfn = __phys_to_pfn(PHYS_PCI_IO_BASE),
154 static void __init ap_map_io(void)
156 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
159 #define INTEGRATOR_SC_VALID_INT 0x003fffff
161 static struct fpga_irq_data sc_irq_data = {
167 static void __init ap_init_irq(void)
169 /* Disable all interrupts initially. */
170 /* Do the core module ones */
171 writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
173 /* do the header card stuff next */
174 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
175 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
177 fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT, &sc_irq_data);
181 static unsigned long ic_irq_enable;
183 static int irq_suspend(void)
185 ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
189 static void irq_resume(void)
191 /* disable all irq sources */
192 writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
193 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
194 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
196 writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
199 #define irq_suspend NULL
200 #define irq_resume NULL
203 static struct syscore_ops irq_syscore_ops = {
204 .suspend = irq_suspend,
205 .resume = irq_resume,
208 static int __init irq_syscore_init(void)
210 register_syscore_ops(&irq_syscore_ops);
215 device_initcall(irq_syscore_init);
220 #define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
221 #define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
222 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
223 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
225 static int ap_flash_init(void)
229 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
231 tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
232 writel(tmp, EBI_CSR1);
234 if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
235 writel(0xa05f, EBI_LOCK);
236 writel(tmp, EBI_CSR1);
242 static void ap_flash_exit(void)
246 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
248 tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
249 writel(tmp, EBI_CSR1);
251 if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
252 writel(0xa05f, EBI_LOCK);
253 writel(tmp, EBI_CSR1);
258 static void ap_flash_set_vpp(int on)
260 void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
262 writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
265 static struct flash_platform_data ap_flash_data = {
266 .map_name = "cfi_probe",
268 .init = ap_flash_init,
269 .exit = ap_flash_exit,
270 .set_vpp = ap_flash_set_vpp,
273 static struct resource cfi_flash_resource = {
274 .start = INTEGRATOR_FLASH_BASE,
275 .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
276 .flags = IORESOURCE_MEM,
279 static struct platform_device cfi_flash_device = {
283 .platform_data = &ap_flash_data,
286 .resource = &cfi_flash_resource,
289 static void __init ap_init(void)
291 unsigned long sc_dec;
294 platform_device_register(&cfi_flash_device);
296 sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
297 for (i = 0; i < 4; i++) {
298 struct lm_device *lmdev;
300 if ((sc_dec & (16 << i)) == 0)
303 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
307 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
308 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
309 lmdev->resource.flags = IORESOURCE_MEM;
310 lmdev->irq = IRQ_AP_EXPINT0 + i;
313 lm_device_register(lmdev);
318 * Where is the timer (VA)?
320 #define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
321 #define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
322 #define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
325 * How long is the timer interval?
327 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
328 #if TIMER_INTERVAL >= 0x100000
329 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
330 #elif TIMER_INTERVAL >= 0x10000
331 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
333 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
336 static unsigned long timer_reload;
338 static void __iomem * const clksrc_base = (void __iomem *)TIMER2_VA_BASE;
340 static cycle_t timersp_read(struct clocksource *cs)
342 return ~(readl(clksrc_base + TIMER_VALUE) & 0xffff);
345 static struct clocksource clocksource_timersp = {
348 .read = timersp_read,
349 .mask = CLOCKSOURCE_MASK(16),
350 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
353 static void integrator_clocksource_init(u32 khz)
355 struct clocksource *cs = &clocksource_timersp;
356 void __iomem *base = clksrc_base;
357 u32 ctrl = TIMER_CTRL_ENABLE;
361 ctrl = TIMER_CTRL_DIV16;
364 writel(ctrl, base + TIMER_CTRL);
365 writel(0xffff, base + TIMER_LOAD);
367 clocksource_register_khz(cs, khz);
370 static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
373 * IRQ handler for the timer
375 static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
377 struct clock_event_device *evt = dev_id;
379 /* clear the interrupt */
380 writel(1, clkevt_base + TIMER_INTCLR);
382 evt->event_handler(evt);
387 static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
389 u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
391 BUG_ON(mode == CLOCK_EVT_MODE_ONESHOT);
393 if (mode == CLOCK_EVT_MODE_PERIODIC) {
394 writel(ctrl, clkevt_base + TIMER_CTRL);
395 writel(timer_reload, clkevt_base + TIMER_LOAD);
396 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
399 writel(ctrl, clkevt_base + TIMER_CTRL);
402 static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
404 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
406 writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
407 writel(next, clkevt_base + TIMER_LOAD);
408 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
413 static struct clock_event_device integrator_clockevent = {
416 .features = CLOCK_EVT_FEAT_PERIODIC,
417 .set_mode = clkevt_set_mode,
418 .set_next_event = clkevt_set_next_event,
420 .cpumask = cpu_all_mask,
423 static struct irqaction integrator_timer_irq = {
425 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
426 .handler = integrator_timer_interrupt,
427 .dev_id = &integrator_clockevent,
430 static void integrator_clockevent_init(u32 khz)
432 struct clock_event_device *evt = &integrator_clockevent;
433 unsigned int ctrl = 0;
435 if (khz * 1000 > 0x100000 * HZ) {
437 ctrl |= TIMER_CTRL_DIV256;
438 } else if (khz * 1000 > 0x10000 * HZ) {
440 ctrl |= TIMER_CTRL_DIV16;
443 timer_reload = khz * 1000 / HZ;
444 writel(ctrl, clkevt_base + TIMER_CTRL);
446 evt->irq = IRQ_TIMERINT1;
447 evt->mult = div_sc(khz, NSEC_PER_MSEC, evt->shift);
448 evt->max_delta_ns = clockevent_delta2ns(0xffff, evt);
449 evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
451 setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
452 clockevents_register_device(evt);
458 static void __init ap_init_timer(void)
460 u32 khz = TICKS_PER_uSEC * 1000;
462 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
463 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
464 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
466 integrator_clocksource_init(khz);
467 integrator_clockevent_init(khz);
470 static struct sys_timer ap_timer = {
471 .init = ap_init_timer,
474 MACHINE_START(INTEGRATOR, "ARM-Integrator")
475 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
476 .boot_params = 0x00000100,
477 .reserve = integrator_reserve,
479 .init_early = integrator_init_early,
480 .init_irq = ap_init_irq,
482 .init_machine = ap_init,