arch/arm/mach-integrator/integrator_ap.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_ap.c
   3  *
   4  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <linux/types.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/device.h>
  25 #include <linux/slab.h>
  26 #include <linux/string.h>
  27 #include <linux/sysdev.h>
  28
  29 #include <asm/hardware.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/setup.h>
  33 #include <asm/mach-types.h>
  34 #include <asm/hardware/amba.h>
  35 #include <asm/hardware/amba_kmi.h>
  36
  37 #include <asm/arch/lm.h>
  38
  39 #include <asm/mach/arch.h>
  40 #include <asm/mach/flash.h>
  41 #include <asm/mach/irq.h>
  42 #include <asm/mach/map.h>
  43 #include <asm/mach/time.h>
  44
  45 #include "common.h"
  46
  47 /*
  48  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  49  * is the (PA >> 12).
  50  *
  51  * Setup a VA for the Integrator interrupt controller (for header #0,
  52  * just for now).
  53  */
  54 #define VA_IC_BASE      IO_ADDRESS(INTEGRATOR_IC_BASE)
  55 #define VA_SC_BASE      IO_ADDRESS(INTEGRATOR_SC_BASE)
  56 #define VA_EBI_BASE     IO_ADDRESS(INTEGRATOR_EBI_BASE)
  57 #define VA_CMIC_BASE    IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_IC_OFFSET
  58
  59 /*
  60  * Logical      Physical
  61  * e8000000     40000000        PCI memory              PHYS_PCI_MEM_BASE       (max 512M)
  62  * ec000000     61000000        PCI config space        PHYS_PCI_CONFIG_BASE    (max 16M)
  63  * ed000000     62000000        PCI V3 regs             PHYS_PCI_V3_BASE        (max 64k)
  64  * ee000000     60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
  65  * ef000000                     Cache flush
  66  * f1000000     10000000        Core module registers
  67  * f1100000     11000000        System controller registers
  68  * f1200000     12000000        EBI registers
  69  * f1300000     13000000        Counter/Timer
  70  * f1400000     14000000        Interrupt controller
  71  * f1600000     16000000        UART 0
  72  * f1700000     17000000        UART 1
  73  * f1a00000     1a000000        Debug LEDs
  74  * f1b00000     1b000000        GPIO
  75  */
  76
  77 static struct map_desc ap_io_desc[] __initdata = {
  78         {
  79                 .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
  80                 .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
  81                 .length         = SZ_4K,
  82                 .type           = MT_DEVICE
  83         }, {
  84                 .virtual        = IO_ADDRESS(INTEGRATOR_SC_BASE),
  85                 .pfn            = __phys_to_pfn(INTEGRATOR_SC_BASE),
  86                 .length         = SZ_4K,
  87                 .type           = MT_DEVICE
  88         }, {
  89                 .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
  90                 .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
  91                 .length         = SZ_4K,
  92                 .type           = MT_DEVICE
  93         }, {
  94                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
  95                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
  96                 .length         = SZ_4K,
  97                 .type           = MT_DEVICE
  98         }, {
  99                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
 100                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
 101                 .length         = SZ_4K,
 102                 .type           = MT_DEVICE
 103         }, {
 104                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
 105                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
 106                 .length         = SZ_4K,
 107                 .type           = MT_DEVICE
 108         }, {
 109                 .virtual        = IO_ADDRESS(INTEGRATOR_UART1_BASE),
 110                 .pfn            = __phys_to_pfn(INTEGRATOR_UART1_BASE),
 111                 .length         = SZ_4K,
 112                 .type           = MT_DEVICE
 113         }, {
 114                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
 115                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
 116                 .length         = SZ_4K,
 117                 .type           = MT_DEVICE
 118         }, {
 119                 .virtual        = IO_ADDRESS(INTEGRATOR_GPIO_BASE),
 120                 .pfn            = __phys_to_pfn(INTEGRATOR_GPIO_BASE),
 121                 .length         = SZ_4K,
 122                 .type           = MT_DEVICE
 123         }, {
 124                 .virtual        = PCI_MEMORY_VADDR,
 125                 .pfn            = __phys_to_pfn(PHYS_PCI_MEM_BASE),
 126                 .length         = SZ_16M,
 127                 .type           = MT_DEVICE
 128         }, {
 129                 .virtual        = PCI_CONFIG_VADDR,
 130                 .pfn            = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
 131                 .length         = SZ_16M,
 132                 .type           = MT_DEVICE
 133         }, {
 134                 .virtual        = PCI_V3_VADDR,
 135                 .pfn            = __phys_to_pfn(PHYS_PCI_V3_BASE),
 136                 .length         = SZ_64K,
 137                 .type           = MT_DEVICE
 138         }, {
 139                 .virtual        = PCI_IO_VADDR,
 140                 .pfn            = __phys_to_pfn(PHYS_PCI_IO_BASE),
 141                 .length         = SZ_64K,
 142                 .type           = MT_DEVICE
 143         }
 144 };
 145
 146 static void __init ap_map_io(void)
 147 {
 148         iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
 149 }
 150
 151 #define INTEGRATOR_SC_VALID_INT 0x003fffff
 152
 153 static void sc_mask_irq(unsigned int irq)
 154 {
 155         writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 156 }
 157
 158 static void sc_unmask_irq(unsigned int irq)
 159 {
 160         writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_SET);
 161 }
 162
 163 static struct irqchip sc_chip = {
 164         .ack    = sc_mask_irq,
 165         .mask   = sc_mask_irq,
 166         .unmask = sc_unmask_irq,
 167 };
 168
 169 static void __init ap_init_irq(void)
 170 {
 171         unsigned int i;
 172
 173         /* Disable all interrupts initially. */
 174         /* Do the core module ones */
 175         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 176
 177         /* do the header card stuff next */
 178         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 179         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 180
 181         for (i = 0; i < NR_IRQS; i++) {
 182                 if (((1 << i) & INTEGRATOR_SC_VALID_INT) != 0) {
 183                         set_irq_chip(i, &sc_chip);
 184                         set_irq_handler(i, do_level_IRQ);
 185                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 186                 }
 187         }
 188 }
 189
 190 #ifdef CONFIG_PM
 191 static unsigned long ic_irq_enable;
 192
 193 static int irq_suspend(struct sys_device *dev, pm_message_t state)
 194 {
 195         ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
 196         return 0;
 197 }
 198
 199 static int irq_resume(struct sys_device *dev)
 200 {
 201         /* disable all irq sources */
 202         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 203         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 204         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 205
 206         writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
 207         return 0;
 208 }
 209 #else
 210 #define irq_suspend NULL
 211 #define irq_resume NULL
 212 #endif
 213
 214 static struct sysdev_class irq_class = {
 215         set_kset_name("irq"),
 216         .suspend        = irq_suspend,
 217         .resume         = irq_resume,
 218 };
 219
 220 static struct sys_device irq_device = {
 221         .id     = 0,
 222         .cls    = &irq_class,
 223 };
 224
 225 static int __init irq_init_sysfs(void)
 226 {
 227         int ret = sysdev_class_register(&irq_class);
 228         if (ret == 0)
 229                 ret = sysdev_register(&irq_device);
 230         return ret;
 231 }
 232
 233 device_initcall(irq_init_sysfs);
 234
 235 /*
 236  * Flash handling.
 237  */
 238 #define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
 239 #define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
 240 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
 241 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
 242
 243 static int ap_flash_init(void)
 244 {
 245         u32 tmp;
 246
 247         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 248
 249         tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
 250         writel(tmp, EBI_CSR1);
 251
 252         if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
 253                 writel(0xa05f, EBI_LOCK);
 254                 writel(tmp, EBI_CSR1);
 255                 writel(0, EBI_LOCK);
 256         }
 257         return 0;
 258 }
 259
 260 static void ap_flash_exit(void)
 261 {
 262         u32 tmp;
 263
 264         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 265
 266         tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
 267         writel(tmp, EBI_CSR1);
 268
 269         if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
 270                 writel(0xa05f, EBI_LOCK);
 271                 writel(tmp, EBI_CSR1);
 272                 writel(0, EBI_LOCK);
 273         }
 274 }
 275
 276 static void ap_flash_set_vpp(int on)
 277 {
 278         unsigned long reg = on ? SC_CTRLS : SC_CTRLC;
 279
 280         writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
 281 }
 282
 283 static struct flash_platform_data ap_flash_data = {
 284         .map_name       = "cfi_probe",
 285         .width          = 4,
 286         .init           = ap_flash_init,
 287         .exit           = ap_flash_exit,
 288         .set_vpp        = ap_flash_set_vpp,
 289 };
 290
 291 static struct resource cfi_flash_resource = {
 292         .start          = INTEGRATOR_FLASH_BASE,
 293         .end            = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
 294         .flags          = IORESOURCE_MEM,
 295 };
 296
 297 static struct platform_device cfi_flash_device = {
 298         .name           = "armflash",
 299         .id             = 0,
 300         .dev            = {
 301                 .platform_data  = &ap_flash_data,
 302         },
 303         .num_resources  = 1,
 304         .resource       = &cfi_flash_resource,
 305 };
 306
 307 static void __init ap_init(void)
 308 {
 309         unsigned long sc_dec;
 310         int i;
 311
 312         platform_device_register(&cfi_flash_device);
 313
 314         sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
 315         for (i = 0; i < 4; i++) {
 316                 struct lm_device *lmdev;
 317
 318                 if ((sc_dec & (16 << i)) == 0)
 319                         continue;
 320
 321                 lmdev = kmalloc(sizeof(struct lm_device), GFP_KERNEL);
 322                 if (!lmdev)
 323                         continue;
 324
 325                 memset(lmdev, 0, sizeof(struct lm_device));
 326
 327                 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
 328                 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
 329                 lmdev->resource.flags = IORESOURCE_MEM;
 330                 lmdev->irq = IRQ_AP_EXPINT0 + i;
 331                 lmdev->id = i;
 332
 333                 lm_device_register(lmdev);
 334         }
 335 }
 336
 337 static void __init ap_init_timer(void)
 338 {
 339         integrator_time_init(1000000 * TICKS_PER_uSEC / HZ, 0);
 340 }
 341
 342 static struct sys_timer ap_timer = {
 343         .init           = ap_init_timer,
 344         .offset         = integrator_gettimeoffset,
 345 };
 346
 347 MACHINE_START(INTEGRATOR, "ARM-Integrator")
 348         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 349         .phys_ram       = 0x00000000,
 350         .phys_io        = 0x16000000,
 351         .io_pg_offst    = ((0xf1600000) >> 18) & 0xfffc,
 352         .boot_params    = 0x00000100,
 353         .map_io         = ap_map_io,
 354         .init_irq       = ap_init_irq,
 355         .timer          = &ap_timer,
 356         .init_machine   = ap_init,
 357 MACHINE_END