2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MX31 specific definitions
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/init.h>
21 #include <linux/err.h>
23 #include <asm/pgtable.h>
24 #include <asm/hardware/cache-l2x0.h>
25 #include <asm/mach/map.h>
27 #include <mach/common.h>
28 #include <mach/devices-common.h>
29 #include <mach/hardware.h>
30 #include <mach/iomux-v3.h>
31 #include <mach/irqs.h>
33 static void imx3_idle(void)
35 unsigned long reg = 0;
38 /* disable I and D cache */
39 "mrc p15, 0, %0, c1, c0, 0\n"
40 "bic %0, %0, #0x00001000\n"
41 "bic %0, %0, #0x00000004\n"
42 "mcr p15, 0, %0, c1, c0, 0\n"
43 /* invalidate I cache */
45 "mcr p15, 0, %0, c7, c5, 0\n"
46 /* clear and invalidate D cache */
48 "mcr p15, 0, %0, c7, c14, 0\n"
51 "mcr p15, 0, %0, c7, c0, 4\n"
52 "nop\n" "nop\n" "nop\n" "nop\n"
53 "nop\n" "nop\n" "nop\n"
54 /* enable I and D cache */
55 "mrc p15, 0, %0, c1, c0, 0\n"
56 "orr %0, %0, #0x00001000\n"
57 "orr %0, %0, #0x00000004\n"
58 "mcr p15, 0, %0, c1, c0, 0\n"
62 static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
65 if (mtype == MT_DEVICE) {
67 * Access all peripherals below 0x80000000 as nonshared device
68 * on mx3, but leave l2cc alone. Otherwise cache corruptions
71 if (phys_addr < 0x80000000 &&
72 !addr_in_module(phys_addr, MX3x_L2CC))
73 mtype = MT_DEVICE_NONSHARED;
76 return __arm_ioremap(phys_addr, size, mtype);
79 void imx3_init_l2x0(void)
81 void __iomem *l2x0_base;
82 void __iomem *clkctl_base;
85 * First of all, we must repair broken chip settings. There are some
86 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
87 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
88 * Workaraound is to setup the correct register setting prior enabling the
89 * L2 cache. This should not hurt already working CPUs, as they are using the
92 #define L2_MEM_VAL 0x10
94 clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
95 if (clkctl_base != NULL) {
96 writel(0x00000515, clkctl_base + L2_MEM_VAL);
99 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
102 l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
103 if (IS_ERR(l2x0_base)) {
104 printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
109 l2x0_init(l2x0_base, 0x00030024, 0x00000000);
112 #ifdef CONFIG_SOC_IMX31
113 static struct map_desc mx31_io_desc[] __initdata = {
114 imx_map_entry(MX31, X_MEMC, MT_DEVICE),
115 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
116 imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
117 imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
118 imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
122 * This function initializes the memory map. It is called during the
123 * system startup to create static physical to virtual memory mappings
124 * for the IO modules.
126 void __init mx31_map_io(void)
128 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
131 void __init imx31_init_early(void)
133 mxc_set_cpu_type(MXC_CPU_MX31);
134 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
135 imx_ioremap = imx3_ioremap;
136 arm_pm_idle = imx3_idle;
139 void __init mx31_init_irq(void)
141 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
144 static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
145 .per_2_per_addr = 1677,
148 static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
151 .bp_2_ap_addr = 1029,
154 static struct sdma_platform_data imx31_sdma_pdata __initdata = {
155 .fw_name = "sdma-imx31-to2.bin",
156 .script_addrs = &imx31_to2_sdma_script,
159 static const struct resource imx31_audmux_res[] __initconst = {
160 DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K),
163 void __init imx31_soc_init(void)
165 int to_version = mx31_revision() >> 4;
169 mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
170 mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
171 mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
173 if (to_version == 1) {
174 strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
175 strlen(imx31_sdma_pdata.fw_name));
176 imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
179 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
180 platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
181 ARRAY_SIZE(imx31_audmux_res));
183 #endif /* ifdef CONFIG_SOC_IMX31 */
185 #ifdef CONFIG_SOC_IMX35
186 static struct map_desc mx35_io_desc[] __initdata = {
187 imx_map_entry(MX35, X_MEMC, MT_DEVICE),
188 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
189 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
190 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
191 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
194 void __init mx35_map_io(void)
196 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
199 void __init imx35_init_early(void)
201 mxc_set_cpu_type(MXC_CPU_MX35);
202 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
203 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
204 arm_pm_idle = imx3_idle;
205 imx_ioremap = imx3_ioremap;
208 void __init mx35_init_irq(void)
210 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
213 static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
215 .uart_2_mcu_addr = 817,
216 .mcu_2_app_addr = 747,
217 .uartsh_2_mcu_addr = 1183,
218 .per_2_shp_addr = 1033,
219 .mcu_2_shp_addr = 961,
220 .ata_2_mcu_addr = 1333,
221 .mcu_2_ata_addr = 1252,
222 .app_2_mcu_addr = 683,
223 .shp_2_per_addr = 1111,
224 .shp_2_mcu_addr = 892,
227 static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
229 .uart_2_mcu_addr = 904,
230 .per_2_app_addr = 1597,
231 .mcu_2_app_addr = 834,
232 .uartsh_2_mcu_addr = 1270,
233 .per_2_shp_addr = 1120,
234 .mcu_2_shp_addr = 1048,
235 .ata_2_mcu_addr = 1429,
236 .mcu_2_ata_addr = 1339,
237 .app_2_per_addr = 1531,
238 .app_2_mcu_addr = 770,
239 .shp_2_per_addr = 1198,
240 .shp_2_mcu_addr = 979,
243 static struct sdma_platform_data imx35_sdma_pdata __initdata = {
244 .fw_name = "sdma-imx35-to2.bin",
245 .script_addrs = &imx35_to2_sdma_script,
248 static const struct resource imx35_audmux_res[] __initconst = {
249 DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K),
252 void __init imx35_soc_init(void)
254 int to_version = mx35_revision() >> 4;
258 /* i.mx35 has the i.mx31 type gpio */
259 mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
260 mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
261 mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
263 if (to_version == 1) {
264 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
265 strlen(imx35_sdma_pdata.fw_name));
266 imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
269 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
270 /* i.mx35 has the i.mx31 type audmux */
271 platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res,
272 ARRAY_SIZE(imx35_audmux_res));
274 #endif /* ifdef CONFIG_SOC_IMX35 */