arch/arm/mach-imx/mach-mx27ads.c

   1 /*
   2  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   3  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   4  *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/platform_device.h>
  18 #include <linux/mtd/mtd.h>
  19 #include <linux/mtd/map.h>
  20 #include <linux/mtd/partitions.h>
  21 #include <linux/mtd/physmap.h>
  22 #include <linux/i2c.h>
  23 #include <linux/irq.h>
  24 #include <mach/common.h>
  25 #include <mach/hardware.h>
  26 #include <asm/mach-types.h>
  27 #include <asm/mach/arch.h>
  28 #include <asm/mach/time.h>
  29 #include <asm/mach/map.h>
  30 #include <mach/gpio.h>
  31 #include <mach/iomux-mx27.h>
  32 #include <mach/mxc_nand.h>
  33
  34 #include "devices-imx27.h"
  35 #include "devices.h"
  36
  37 /*
  38  * Base address of PBC controller, CS4
  39  */
  40 #define PBC_BASE_ADDRESS        0xf4300000
  41 #define PBC_REG_ADDR(offset)    (void __force __iomem *) \
  42                 (PBC_BASE_ADDRESS + (offset))
  43
  44 /* When the PBC address connection is fixed in h/w, defined as 1 */
  45 #define PBC_ADDR_SH             0
  46
  47 /* Offsets for the PBC Controller register */
  48 /*
  49  * PBC Board version register offset
  50  */
  51 #define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
  52 /*
  53  * PBC Board control register 1 set address.
  54  */
  55 #define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
  56 /*
  57  * PBC Board control register 1 clear address.
  58  */
  59 #define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
  60
  61 /* PBC Board Control Register 1 bit definitions */
  62 #define PBC_BCTRL1_LCDON        0x0800  /* Enable the LCD */
  63
  64 /* to determine the correct external crystal reference */
  65 #define CKIH_27MHZ_BIT_SET      (1 << 3)
  66
  67 static const int mx27ads_pins[] __initconst = {
  68         /* UART0 */
  69         PE12_PF_UART1_TXD,
  70         PE13_PF_UART1_RXD,
  71         PE14_PF_UART1_CTS,
  72         PE15_PF_UART1_RTS,
  73         /* UART1 */
  74         PE3_PF_UART2_CTS,
  75         PE4_PF_UART2_RTS,
  76         PE6_PF_UART2_TXD,
  77         PE7_PF_UART2_RXD,
  78         /* UART2 */
  79         PE8_PF_UART3_TXD,
  80         PE9_PF_UART3_RXD,
  81         PE10_PF_UART3_CTS,
  82         PE11_PF_UART3_RTS,
  83         /* UART3 */
  84         PB26_AF_UART4_RTS,
  85         PB28_AF_UART4_TXD,
  86         PB29_AF_UART4_CTS,
  87         PB31_AF_UART4_RXD,
  88         /* UART4 */
  89         PB18_AF_UART5_TXD,
  90         PB19_AF_UART5_RXD,
  91         PB20_AF_UART5_CTS,
  92         PB21_AF_UART5_RTS,
  93         /* UART5 */
  94         PB10_AF_UART6_TXD,
  95         PB12_AF_UART6_CTS,
  96         PB11_AF_UART6_RXD,
  97         PB13_AF_UART6_RTS,
  98         /* FEC */
  99         PD0_AIN_FEC_TXD0,
 100         PD1_AIN_FEC_TXD1,
 101         PD2_AIN_FEC_TXD2,
 102         PD3_AIN_FEC_TXD3,
 103         PD4_AOUT_FEC_RX_ER,
 104         PD5_AOUT_FEC_RXD1,
 105         PD6_AOUT_FEC_RXD2,
 106         PD7_AOUT_FEC_RXD3,
 107         PD8_AF_FEC_MDIO,
 108         PD9_AIN_FEC_MDC,
 109         PD10_AOUT_FEC_CRS,
 110         PD11_AOUT_FEC_TX_CLK,
 111         PD12_AOUT_FEC_RXD0,
 112         PD13_AOUT_FEC_RX_DV,
 113         PD14_AOUT_FEC_RX_CLK,
 114         PD15_AOUT_FEC_COL,
 115         PD16_AIN_FEC_TX_ER,
 116         PF23_AIN_FEC_TX_EN,
 117         /* I2C2 */
 118         PC5_PF_I2C2_SDA,
 119         PC6_PF_I2C2_SCL,
 120         /* FB */
 121         PA5_PF_LSCLK,
 122         PA6_PF_LD0,
 123         PA7_PF_LD1,
 124         PA8_PF_LD2,
 125         PA9_PF_LD3,
 126         PA10_PF_LD4,
 127         PA11_PF_LD5,
 128         PA12_PF_LD6,
 129         PA13_PF_LD7,
 130         PA14_PF_LD8,
 131         PA15_PF_LD9,
 132         PA16_PF_LD10,
 133         PA17_PF_LD11,
 134         PA18_PF_LD12,
 135         PA19_PF_LD13,
 136         PA20_PF_LD14,
 137         PA21_PF_LD15,
 138         PA22_PF_LD16,
 139         PA23_PF_LD17,
 140         PA24_PF_REV,
 141         PA25_PF_CLS,
 142         PA26_PF_PS,
 143         PA27_PF_SPL_SPR,
 144         PA28_PF_HSYNC,
 145         PA29_PF_VSYNC,
 146         PA30_PF_CONTRAST,
 147         PA31_PF_OE_ACD,
 148         /* OWIRE */
 149         PE16_AF_OWIRE,
 150         /* SDHC1*/
 151         PE18_PF_SD1_D0,
 152         PE19_PF_SD1_D1,
 153         PE20_PF_SD1_D2,
 154         PE21_PF_SD1_D3,
 155         PE22_PF_SD1_CMD,
 156         PE23_PF_SD1_CLK,
 157         /* SDHC2*/
 158         PB4_PF_SD2_D0,
 159         PB5_PF_SD2_D1,
 160         PB6_PF_SD2_D2,
 161         PB7_PF_SD2_D3,
 162         PB8_PF_SD2_CMD,
 163         PB9_PF_SD2_CLK,
 164 };
 165
 166 static const struct mxc_nand_platform_data
 167 mx27ads_nand_board_info __initconst = {
 168         .width = 1,
 169         .hw_ecc = 1,
 170 };
 171
 172 /* ADS's NOR flash */
 173 static struct physmap_flash_data mx27ads_flash_data = {
 174         .width = 2,
 175 };
 176
 177 static struct resource mx27ads_flash_resource = {
 178         .start = 0xc0000000,
 179         .end = 0xc0000000 + 0x02000000 - 1,
 180         .flags = IORESOURCE_MEM,
 181
 182 };
 183
 184 static struct platform_device mx27ads_nor_mtd_device = {
 185         .name = "physmap-flash",
 186         .id = 0,
 187         .dev = {
 188                 .platform_data = &mx27ads_flash_data,
 189         },
 190         .num_resources = 1,
 191         .resource = &mx27ads_flash_resource,
 192 };
 193
 194 static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = {
 195         .bitrate = 100000,
 196 };
 197
 198 static struct i2c_board_info mx27ads_i2c_devices[] = {
 199 };
 200
 201 void lcd_power(int on)
 202 {
 203         if (on)
 204                 __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
 205         else
 206                 __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
 207 }
 208
 209 static struct imx_fb_videomode mx27ads_modes[] = {
 210         {
 211                 .mode = {
 212                         .name           = "Sharp-LQ035Q7",
 213                         .refresh        = 60,
 214                         .xres           = 240,
 215                         .yres           = 320,
 216                         .pixclock       = 188679, /* in ps (5.3MHz) */
 217                         .hsync_len      = 1,
 218                         .left_margin    = 9,
 219                         .right_margin   = 16,
 220                         .vsync_len      = 1,
 221                         .upper_margin   = 7,
 222                         .lower_margin   = 9,
 223                 },
 224                 .bpp            = 16,
 225                 .pcr            = 0xFB008BC0,
 226         },
 227 };
 228
 229 static const struct imx_fb_platform_data mx27ads_fb_data __initconst = {
 230         .mode = mx27ads_modes,
 231         .num_modes = ARRAY_SIZE(mx27ads_modes),
 232
 233         /*
 234          * - HSYNC active high
 235          * - VSYNC active high
 236          * - clk notenabled while idle
 237          * - clock inverted
 238          * - data not inverted
 239          * - data enable low active
 240          * - enable sharp mode
 241          */
 242         .pwmr           = 0x00A903FF,
 243         .lscr1          = 0x00120300,
 244         .dmacr          = 0x00020010,
 245
 246         .lcd_power      = lcd_power,
 247 };
 248
 249 static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
 250                               void *data)
 251 {
 252         return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING,
 253                            "sdhc1-card-detect", data);
 254 }
 255
 256 static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
 257                               void *data)
 258 {
 259         return request_irq(IRQ_GPIOB(7), detect_irq, IRQF_TRIGGER_RISING,
 260                            "sdhc2-card-detect", data);
 261 }
 262
 263 static void mx27ads_sdhc1_exit(struct device *dev, void *data)
 264 {
 265         free_irq(IRQ_GPIOE(21), data);
 266 }
 267
 268 static void mx27ads_sdhc2_exit(struct device *dev, void *data)
 269 {
 270         free_irq(IRQ_GPIOB(7), data);
 271 }
 272
 273 static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
 274         .init = mx27ads_sdhc1_init,
 275         .exit = mx27ads_sdhc1_exit,
 276 };
 277
 278 static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
 279         .init = mx27ads_sdhc2_init,
 280         .exit = mx27ads_sdhc2_exit,
 281 };
 282
 283 static struct platform_device *platform_devices[] __initdata = {
 284         &mx27ads_nor_mtd_device,
 285 };
 286
 287 static const struct imxuart_platform_data uart_pdata __initconst = {
 288         .flags = IMXUART_HAVE_RTSCTS,
 289 };
 290
 291 static void __init mx27ads_board_init(void)
 292 {
 293         mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
 294                         "mx27ads");
 295
 296         imx27_add_imx_uart0(&uart_pdata);
 297         imx27_add_imx_uart1(&uart_pdata);
 298         imx27_add_imx_uart2(&uart_pdata);
 299         imx27_add_imx_uart3(&uart_pdata);
 300         imx27_add_imx_uart4(&uart_pdata);
 301         imx27_add_imx_uart5(&uart_pdata);
 302         imx27_add_mxc_nand(&mx27ads_nand_board_info);
 303
 304         /* only the i2c master 1 is used on this CPU card */
 305         i2c_register_board_info(1, mx27ads_i2c_devices,
 306                                 ARRAY_SIZE(mx27ads_i2c_devices));
 307         imx27_add_imx_i2c(1, &mx27ads_i2c1_data);
 308         imx27_add_imx_fb(&mx27ads_fb_data);
 309         imx27_add_mxc_mmc(0, &sdhc1_pdata);
 310         imx27_add_mxc_mmc(1, &sdhc2_pdata);
 311
 312         imx27_add_fec(NULL);
 313         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 314         imx27_add_mxc_w1(NULL);
 315 }
 316
 317 static void __init mx27ads_timer_init(void)
 318 {
 319         unsigned long fref = 26000000;
 320
 321         if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
 322                 fref = 27000000;
 323
 324         mx27_clocks_init(fref);
 325 }
 326
 327 static struct sys_timer mx27ads_timer = {
 328         .init   = mx27ads_timer_init,
 329 };
 330
 331 static struct map_desc mx27ads_io_desc[] __initdata = {
 332         {
 333                 .virtual = PBC_BASE_ADDRESS,
 334                 .pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR),
 335                 .length = SZ_1M,
 336                 .type = MT_DEVICE,
 337         },
 338 };
 339
 340 static void __init mx27ads_map_io(void)
 341 {
 342         mx27_map_io();
 343         iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
 344 }
 345
 346 MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
 347         /* maintainer: Freescale Semiconductor, Inc. */
 348         .boot_params    = MX27_PHYS_OFFSET + 0x100,
 349         .map_io         = mx27ads_map_io,
 350         .init_irq       = mx27_init_irq,
 351         .init_machine   = mx27ads_board_init,
 352         .timer          = &mx27ads_timer,
 353 MACHINE_END