arch/arm/mach-imx/imx8m/soc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2019 NXP
   4  *
   5  * Peng Fan <peng.fan@nxp.com>
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <init.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/mach-imx/hab.h>
  16 #include <asm/mach-imx/boot_mode.h>
  17 #include <asm/mach-imx/syscounter.h>
  18 #include <asm/armv8/mmu.h>
  19 #include <dm/uclass.h>
  20 #include <errno.h>
  21 #include <fdt_support.h>
  22 #include <fsl_wdog.h>
  23 #include <imx_sip.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 #if defined(CONFIG_IMX_HAB)
  28 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  29         .bank = 1,
  30         .word = 3,
  31 };
  32 #endif
  33
  34 int timer_init(void)
  35 {
  36 #ifdef CONFIG_SPL_BUILD
  37         struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
  38         unsigned long freq = readl(&sctr->cntfid0);
  39
  40         /* Update with accurate clock frequency */
  41         asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
  42
  43         clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
  44                         SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
  45 #endif
  46
  47         gd->arch.tbl = 0;
  48         gd->arch.tbu = 0;
  49
  50         return 0;
  51 }
  52
  53 void enable_tzc380(void)
  54 {
  55         struct iomuxc_gpr_base_regs *gpr =
  56                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  57
  58         /* Enable TZASC and lock setting */
  59         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
  60         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
  61         if (is_imx8mm() || is_imx8mn() || is_imx8mp())
  62                 setbits_le32(&gpr->gpr[10], BIT(1));
  63         /*
  64          * set Region 0 attribute to allow secure and non-secure
  65          * read/write permission. Found some masters like usb dwc3
  66          * controllers can't work with secure memory.
  67          */
  68         writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
  69 }
  70
  71 void set_wdog_reset(struct wdog_regs *wdog)
  72 {
  73         /*
  74          * Output WDOG_B signal to reset external pmic or POR_B decided by
  75          * the board design. Without external reset, the peripherals/DDR/
  76          * PMIC are not reset, that may cause system working abnormal.
  77          * WDZST bit is write-once only bit. Align this bit in kernel,
  78          * otherwise kernel code will have no chance to set this bit.
  79          */
  80         setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
  81 }
  82
  83 static struct mm_region imx8m_mem_map[] = {
  84         {
  85                 /* ROM */
  86                 .virt = 0x0UL,
  87                 .phys = 0x0UL,
  88                 .size = 0x100000UL,
  89                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  90                          PTE_BLOCK_OUTER_SHARE
  91         }, {
  92                 /* CAAM */
  93                 .virt = 0x100000UL,
  94                 .phys = 0x100000UL,
  95                 .size = 0x8000UL,
  96                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  97                          PTE_BLOCK_NON_SHARE |
  98                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  99         }, {
 100                 /* TCM */
 101                 .virt = 0x7C0000UL,
 102                 .phys = 0x7C0000UL,
 103                 .size = 0x80000UL,
 104                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 105                          PTE_BLOCK_NON_SHARE |
 106                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 107         }, {
 108                 /* OCRAM */
 109                 .virt = 0x900000UL,
 110                 .phys = 0x900000UL,
 111                 .size = 0x200000UL,
 112                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 113                          PTE_BLOCK_OUTER_SHARE
 114         }, {
 115                 /* AIPS */
 116                 .virt = 0xB00000UL,
 117                 .phys = 0xB00000UL,
 118                 .size = 0x3f500000UL,
 119                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 120                          PTE_BLOCK_NON_SHARE |
 121                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 122         }, {
 123                 /* DRAM1 */
 124                 .virt = 0x40000000UL,
 125                 .phys = 0x40000000UL,
 126                 .size = PHYS_SDRAM_SIZE,
 127                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 128                          PTE_BLOCK_OUTER_SHARE
 129 #ifdef PHYS_SDRAM_2_SIZE
 130         }, {
 131                 /* DRAM2 */
 132                 .virt = 0x100000000UL,
 133                 .phys = 0x100000000UL,
 134                 .size = PHYS_SDRAM_2_SIZE,
 135                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 136                          PTE_BLOCK_OUTER_SHARE
 137 #endif
 138         }, {
 139                 /* List terminator */
 140                 0,
 141         }
 142 };
 143
 144 struct mm_region *mem_map = imx8m_mem_map;
 145
 146 void enable_caches(void)
 147 {
 148         /*
 149          * If OPTEE runs, remove OPTEE memory from MMU table to
 150          * avoid speculative prefetch. OPTEE runs at the top of
 151          * the first memory bank
 152          */
 153         if (rom_pointer[1])
 154                 imx8m_mem_map[5].size -= rom_pointer[1];
 155
 156         icache_enable();
 157         dcache_enable();
 158 }
 159
 160 static u32 get_cpu_variant_type(u32 type)
 161 {
 162         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 163         struct fuse_bank *bank = &ocotp->bank[1];
 164         struct fuse_bank1_regs *fuse =
 165                 (struct fuse_bank1_regs *)bank->fuse_regs;
 166
 167         u32 value = readl(&fuse->tester4);
 168
 169         if (type == MXC_CPU_IMX8MQ) {
 170                 if ((value & 0x3) == 0x2)
 171                         return MXC_CPU_IMX8MD;
 172                 else if (value & 0x200000)
 173                         return MXC_CPU_IMX8MQL;
 174
 175         } else if (type == MXC_CPU_IMX8MM) {
 176                 switch (value & 0x3) {
 177                 case 2:
 178                         if (value & 0x1c0000)
 179                                 return MXC_CPU_IMX8MMDL;
 180                         else
 181                                 return MXC_CPU_IMX8MMD;
 182                 case 3:
 183                         if (value & 0x1c0000)
 184                                 return MXC_CPU_IMX8MMSL;
 185                         else
 186                                 return MXC_CPU_IMX8MMS;
 187                 default:
 188                         if (value & 0x1c0000)
 189                                 return MXC_CPU_IMX8MML;
 190                         break;
 191                 }
 192         } else if (type == MXC_CPU_IMX8MN) {
 193                 switch (value & 0x3) {
 194                 case 2:
 195                         if (value & 0x1000000)
 196                                 return MXC_CPU_IMX8MNDL;
 197                         else
 198                                 return MXC_CPU_IMX8MND;
 199                 case 3:
 200                         if (value & 0x1000000)
 201                                 return MXC_CPU_IMX8MNSL;
 202                         else
 203                                 return MXC_CPU_IMX8MNS;
 204                 default:
 205                         if (value & 0x1000000)
 206                                 return MXC_CPU_IMX8MNL;
 207                         break;
 208                 }
 209         }
 210
 211         return type;
 212 }
 213
 214 u32 get_cpu_rev(void)
 215 {
 216         struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
 217         u32 reg = readl(&ana_pll->digprog);
 218         u32 type = (reg >> 16) & 0xff;
 219         u32 major_low = (reg >> 8) & 0xff;
 220         u32 rom_version;
 221
 222         reg &= 0xff;
 223
 224         /* iMX8MP */
 225         if (major_low == 0x43) {
 226                 return (MXC_CPU_IMX8MP << 12) | reg;
 227         } else if (major_low == 0x42) {
 228                 /* iMX8MN */
 229                 type = get_cpu_variant_type(MXC_CPU_IMX8MN);
 230         } else if (major_low == 0x41) {
 231                 type = get_cpu_variant_type(MXC_CPU_IMX8MM);
 232         } else {
 233                 if (reg == CHIP_REV_1_0) {
 234                         /*
 235                          * For B0 chip, the DIGPROG is not updated,
 236                          * it is still TO1.0. we have to check ROM
 237                          * version or OCOTP_READ_FUSE_DATA.
 238                          * 0xff0055aa is magic number for B1.
 239                          */
 240                         if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
 241                                 reg = CHIP_REV_2_1;
 242                         } else {
 243                                 rom_version =
 244                                         readl((void __iomem *)ROM_VERSION_A0);
 245                                 if (rom_version != CHIP_REV_1_0) {
 246                                         rom_version = readl((void __iomem *)ROM_VERSION_B0);
 247                                         rom_version &= 0xff;
 248                                         if (rom_version == CHIP_REV_2_0)
 249                                                 reg = CHIP_REV_2_0;
 250                                 }
 251                         }
 252                 }
 253
 254                 type = get_cpu_variant_type(type);
 255         }
 256
 257         return (type << 12) | reg;
 258 }
 259
 260 static void imx_set_wdog_powerdown(bool enable)
 261 {
 262         struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
 263         struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
 264         struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
 265
 266         /* Write to the PDE (Power Down Enable) bit */
 267         writew(enable, &wdog1->wmcr);
 268         writew(enable, &wdog2->wmcr);
 269         writew(enable, &wdog3->wmcr);
 270 }
 271
 272 int arch_cpu_init_dm(void)
 273 {
 274         struct udevice *dev;
 275         int ret;
 276
 277         if (CONFIG_IS_ENABLED(CLK)) {
 278                 ret = uclass_get_device_by_name(UCLASS_CLK,
 279                                                 "clock-controller@30380000",
 280                                                 &dev);
 281                 if (ret < 0) {
 282                         printf("Failed to find clock node. Check device tree\n");
 283                         return ret;
 284                 }
 285         }
 286
 287         return 0;
 288 }
 289
 290 int arch_cpu_init(void)
 291 {
 292         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 293         /*
 294          * ROM might disable clock for SCTR,
 295          * enable the clock before timer_init.
 296          */
 297         if (IS_ENABLED(CONFIG_SPL_BUILD))
 298                 clock_enable(CCGR_SCTR, 1);
 299         /*
 300          * Init timer at very early state, because sscg pll setting
 301          * will use it
 302          */
 303         timer_init();
 304
 305         if (IS_ENABLED(CONFIG_SPL_BUILD)) {
 306                 clock_init();
 307                 imx_set_wdog_powerdown(false);
 308         }
 309
 310         if (is_imx8mq()) {
 311                 clock_enable(CCGR_OCOTP, 1);
 312                 if (readl(&ocotp->ctrl) & 0x200)
 313                         writel(0x200, &ocotp->ctrl_clr);
 314         }
 315
 316         return 0;
 317 }
 318
 319 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
 320 struct rom_api *g_rom_api = (struct rom_api *)0x980;
 321
 322 enum boot_device get_boot_device(void)
 323 {
 324         volatile gd_t *pgd = gd;
 325         int ret;
 326         u32 boot;
 327         u16 boot_type;
 328         u8 boot_instance;
 329         enum boot_device boot_dev = SD1_BOOT;
 330
 331         ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
 332                                           ((uintptr_t)&boot) ^ QUERY_BT_DEV);
 333         gd = pgd;
 334
 335         if (ret != ROM_API_OKAY) {
 336                 puts("ROMAPI: failure at query_boot_info\n");
 337                 return -1;
 338         }
 339
 340         boot_type = boot >> 16;
 341         boot_instance = (boot >> 8) & 0xff;
 342
 343         switch (boot_type) {
 344         case BT_DEV_TYPE_SD:
 345                 boot_dev = boot_instance + SD1_BOOT;
 346                 break;
 347         case BT_DEV_TYPE_MMC:
 348                 boot_dev = boot_instance + MMC1_BOOT;
 349                 break;
 350         case BT_DEV_TYPE_NAND:
 351                 boot_dev = NAND_BOOT;
 352                 break;
 353         case BT_DEV_TYPE_FLEXSPINOR:
 354                 boot_dev = QSPI_BOOT;
 355                 break;
 356         case BT_DEV_TYPE_USB:
 357                 boot_dev = USB_BOOT;
 358                 break;
 359         default:
 360                 break;
 361         }
 362
 363         return boot_dev;
 364 }
 365 #endif
 366
 367 bool is_usb_boot(void)
 368 {
 369         return get_boot_device() == USB_BOOT;
 370 }
 371
 372 #ifdef CONFIG_OF_SYSTEM_SETUP
 373 int ft_system_setup(void *blob, bd_t *bd)
 374 {
 375         int i = 0;
 376         int rc;
 377         int nodeoff;
 378
 379         /* Disable the CPU idle for A0 chip since the HW does not support it */
 380         if (is_soc_rev(CHIP_REV_1_0)) {
 381                 static const char * const nodes_path[] = {
 382                         "/cpus/cpu@0",
 383                         "/cpus/cpu@1",
 384                         "/cpus/cpu@2",
 385                         "/cpus/cpu@3",
 386                 };
 387
 388                 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
 389                         nodeoff = fdt_path_offset(blob, nodes_path[i]);
 390                         if (nodeoff < 0)
 391                                 continue; /* Not found, skip it */
 392
 393                         debug("Found %s node\n", nodes_path[i]);
 394
 395                         rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
 396                         if (rc == -FDT_ERR_NOTFOUND)
 397                                 continue;
 398                         if (rc) {
 399                                 printf("Unable to update property %s:%s, err=%s\n",
 400                                        nodes_path[i], "status", fdt_strerror(rc));
 401                                 return rc;
 402                         }
 403
 404                         debug("Remove %s:%s\n", nodes_path[i],
 405                                "cpu-idle-states");
 406                 }
 407         }
 408
 409         return 0;
 410 }
 411 #endif
 412
 413 #if !CONFIG_IS_ENABLED(SYSRESET)
 414 void reset_cpu(ulong addr)
 415 {
 416         struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
 417
 418         /* Clear WDA to trigger WDOG_B immediately */
 419         writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
 420
 421         while (1) {
 422                 /*
 423                  * spin for .5 seconds before reset
 424                  */
 425         }
 426 }
 427 #endif
 428
 429 #if defined(CONFIG_ARCH_MISC_INIT)
 430 static void acquire_buildinfo(void)
 431 {
 432         u64 atf_commit = 0;
 433
 434         /* Get ARM Trusted Firmware commit id */
 435         atf_commit = call_imx_sip(IMX_SIP_BUILDINFO,
 436                                   IMX_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0);
 437         if (atf_commit == 0xffffffff) {
 438                 debug("ATF does not support build info\n");
 439                 atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */
 440         }
 441
 442         printf("\n BuildInfo:\n  - ATF %s\n\n", (char *)&atf_commit);
 443 }
 444
 445 int arch_misc_init(void)
 446 {
 447         acquire_buildinfo();
 448
 449         return 0;
 450 }
 451 #endif
 452
 453 void imx_tmu_arch_init(void *reg_base)
 454 {
 455         if (is_imx8mm() || is_imx8mn()) {
 456                 /* Load TCALIV and TASR from fuses */
 457                 struct ocotp_regs *ocotp =
 458                         (struct ocotp_regs *)OCOTP_BASE_ADDR;
 459                 struct fuse_bank *bank = &ocotp->bank[3];
 460                 struct fuse_bank3_regs *fuse =
 461                         (struct fuse_bank3_regs *)bank->fuse_regs;
 462
 463                 u32 tca_rt, tca_hr, tca_en;
 464                 u32 buf_vref, buf_slope;
 465
 466                 tca_rt = fuse->ana0 & 0xFF;
 467                 tca_hr = (fuse->ana0 & 0xFF00) >> 8;
 468                 tca_en = (fuse->ana0 & 0x2000000) >> 25;
 469
 470                 buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
 471                 buf_slope = (fuse->ana0 & 0xF0000) >> 16;
 472
 473                 writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
 474                 writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
 475                        (ulong)reg_base + 0x30);
 476         }
 477 #ifdef CONFIG_IMX8MP
 478         /* Load TCALIV0/1/m40 and TRIM from fuses */
 479         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 480         struct fuse_bank *bank = &ocotp->bank[38];
 481         struct fuse_bank38_regs *fuse =
 482                 (struct fuse_bank38_regs *)bank->fuse_regs;
 483         struct fuse_bank *bank2 = &ocotp->bank[39];
 484         struct fuse_bank39_regs *fuse2 =
 485                 (struct fuse_bank39_regs *)bank2->fuse_regs;
 486         u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr;
 487         u32 reg;
 488         u32 tca40[2], tca25[2], tca105[2];
 489
 490         /* For blank sample */
 491         if (!fuse->ana_trim2 && !fuse->ana_trim3 &&
 492             !fuse->ana_trim4 && !fuse2->ana_trim5) {
 493                 /* Use a default 25C binary codes */
 494                 tca25[0] = 1596;
 495                 tca25[1] = 1596;
 496                 writel(tca25[0], (ulong)reg_base + 0x30);
 497                 writel(tca25[1], (ulong)reg_base + 0x34);
 498                 return;
 499         }
 500
 501         buf_vref = (fuse->ana_trim2 & 0xc0) >> 6;
 502         buf_slope = (fuse->ana_trim2 & 0xF00) >> 8;
 503         bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12;
 504         bgr = (fuse->ana_trim2 & 0xF0000) >> 16;
 505         vlsb = (fuse->ana_trim2 & 0xF00000) >> 20;
 506         writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
 507
 508         reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | (1 << 7);
 509         writel(reg, (ulong)reg_base + 0x3c);
 510
 511         tca40[0] = (fuse->ana_trim3 & 0xFFF0000) >> 16;
 512         tca25[0] = (fuse->ana_trim3 & 0xF0000000) >> 28;
 513         tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4);
 514         tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8;
 515         tca40[1] = (fuse->ana_trim4 & 0xFFF00000) >> 20;
 516         tca25[1] = fuse2->ana_trim5 & 0xFFF;
 517         tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12;
 518
 519         /* use 25c for 1p calibration */
 520         writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30);
 521         writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34);
 522         writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
 523 #endif
 524 }