1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
5 * Peng Fan <peng.fan@nxp.com>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/sys_proto.h>
15 #include <linux/delay.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
21 void enable_ocotp_clk(unsigned char enable)
23 clock_enable(CCGR_OCOTP, !!enable);
26 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
28 /* 0 - 3 is valid i2c num */
32 clock_enable(CCGR_I2C1 + i2c_num, !!enable);
37 #ifdef CONFIG_SPL_BUILD
38 static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
39 PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
40 PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
41 PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
42 PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
43 PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
44 PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
45 PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
46 PLL_1443X_RATE(266666667U, 400, 9, 2, 0),
47 PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
48 PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
51 static int fracpll_configure(enum pll_clocks pll, u32 freq)
56 struct imx_int_pll_rate_table *rate;
58 for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) {
59 if (freq == imx8mm_fracpll_tbl[i].rate)
63 if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
64 printf("No matched freq table %u\n", freq);
68 rate = &imx8mm_fracpll_tbl[i];
72 setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
73 setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
74 writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
76 pll_base = &ana_pll->dram_pll_gnrl_ctl;
78 case ANATOP_VIDEO_PLL:
79 pll_base = &ana_pll->video_pll1_gnrl_ctl;
84 /* Bypass clock and set lock to pll output lock */
85 tmp = readl(pll_base);
87 writel(tmp, pll_base);
91 writel(tmp, pll_base);
93 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
94 (rate->sdiv << SDIV_SHIFT);
95 writel(div_val, pll_base + 4);
96 writel(rate->kdiv << KDIV_SHIFT, pll_base + 8);
102 writel(tmp, pll_base);
105 while (!(readl(pll_base) & LOCK_STATUS))
110 writel(tmp, pll_base);
115 void dram_pll_init(ulong pll_val)
117 fracpll_configure(ANATOP_DRAM_PLL, pll_val);
120 static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] = {
121 DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
123 DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
125 DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
129 void dram_enable_bypass(ulong clk_val)
132 struct dram_bypass_clk_setting *config;
134 for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++) {
135 if (clk_val == imx8mm_dram_bypass_tbl[i].clk)
139 if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
140 printf("No matched freq table %lu\n", clk_val);
144 config = &imx8mm_dram_bypass_tbl[i];
146 clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
147 CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
148 CLK_ROOT_PRE_DIV(config->alt_pre_div));
149 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
150 CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
151 CLK_ROOT_PRE_DIV(config->apb_pre_div));
152 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
153 CLK_ROOT_SOURCE_SEL(1));
156 void dram_disable_bypass(void)
158 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
159 CLK_ROOT_SOURCE_SEL(0));
160 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
161 CLK_ROOT_SOURCE_SEL(4) |
162 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
166 void init_uart_clk(u32 index)
169 * set uart clock root
174 clock_enable(CCGR_UART1, 0);
175 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
176 CLK_ROOT_SOURCE_SEL(0));
177 clock_enable(CCGR_UART1, 1);
180 clock_enable(CCGR_UART2, 0);
181 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
182 CLK_ROOT_SOURCE_SEL(0));
183 clock_enable(CCGR_UART2, 1);
186 clock_enable(CCGR_UART3, 0);
187 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
188 CLK_ROOT_SOURCE_SEL(0));
189 clock_enable(CCGR_UART3, 1);
192 clock_enable(CCGR_UART4, 0);
193 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
194 CLK_ROOT_SOURCE_SEL(0));
195 clock_enable(CCGR_UART4, 1);
198 printf("Invalid uart index\n");
203 void init_wdog_clk(void)
205 clock_enable(CCGR_WDOG1, 0);
206 clock_enable(CCGR_WDOG2, 0);
207 clock_enable(CCGR_WDOG3, 0);
208 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
209 CLK_ROOT_SOURCE_SEL(0));
210 clock_enable(CCGR_WDOG1, 1);
211 clock_enable(CCGR_WDOG2, 1);
212 clock_enable(CCGR_WDOG3, 1);
220 * The gate is not exported to clk tree, so configure them here.
221 * According to ANAMIX SPEC
222 * sys pll1 fixed at 800MHz
223 * sys pll2 fixed at 1GHz
224 * Here we only enable the outputs.
226 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl);
227 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
228 INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
229 INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
230 INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
231 INTPLL_DIV20_CLKE_MASK;
232 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl);
234 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl);
235 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
236 INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
237 INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
238 INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
239 INTPLL_DIV20_CLKE_MASK;
240 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl);
242 /* config GIC to sys_pll2_100m */
243 clock_enable(CCGR_GIC, 0);
244 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
245 CLK_ROOT_SOURCE_SEL(3));
246 clock_enable(CCGR_GIC, 1);
248 clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
249 CLK_ROOT_SOURCE_SEL(1));
251 clock_enable(CCGR_DDR1, 0);
252 clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
253 CLK_ROOT_SOURCE_SEL(1));
254 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
255 CLK_ROOT_SOURCE_SEL(1));
256 clock_enable(CCGR_DDR1, 1);
260 clock_enable(CCGR_TEMP_SENSOR, 1);
262 clock_enable(CCGR_SEC_DEBUG, 1);
267 u32 imx_get_uartclk(void)
272 static u32 decode_intpll(enum clk_root_src intpll)
274 u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask;
275 u32 main_div, pre_div, post_div, div;
280 pll_gnrl_ctl = readl(&ana_pll->arm_pll_gnrl_ctl);
281 pll_div_ctl = readl(&ana_pll->arm_pll_div_ctl);
284 pll_gnrl_ctl = readl(&ana_pll->gpu_pll_gnrl_ctl);
285 pll_div_ctl = readl(&ana_pll->gpu_pll_div_ctl);
288 pll_gnrl_ctl = readl(&ana_pll->vpu_pll_gnrl_ctl);
289 pll_div_ctl = readl(&ana_pll->vpu_pll_div_ctl);
291 case SYSTEM_PLL1_800M_CLK:
292 case SYSTEM_PLL1_400M_CLK:
293 case SYSTEM_PLL1_266M_CLK:
294 case SYSTEM_PLL1_200M_CLK:
295 case SYSTEM_PLL1_160M_CLK:
296 case SYSTEM_PLL1_133M_CLK:
297 case SYSTEM_PLL1_100M_CLK:
298 case SYSTEM_PLL1_80M_CLK:
299 case SYSTEM_PLL1_40M_CLK:
300 pll_gnrl_ctl = readl(&ana_pll->sys_pll1_gnrl_ctl);
301 pll_div_ctl = readl(&ana_pll->sys_pll1_div_ctl);
303 case SYSTEM_PLL2_1000M_CLK:
304 case SYSTEM_PLL2_500M_CLK:
305 case SYSTEM_PLL2_333M_CLK:
306 case SYSTEM_PLL2_250M_CLK:
307 case SYSTEM_PLL2_200M_CLK:
308 case SYSTEM_PLL2_166M_CLK:
309 case SYSTEM_PLL2_125M_CLK:
310 case SYSTEM_PLL2_100M_CLK:
311 case SYSTEM_PLL2_50M_CLK:
312 pll_gnrl_ctl = readl(&ana_pll->sys_pll2_gnrl_ctl);
313 pll_div_ctl = readl(&ana_pll->sys_pll2_div_ctl);
315 case SYSTEM_PLL3_CLK:
316 pll_gnrl_ctl = readl(&ana_pll->sys_pll3_gnrl_ctl);
317 pll_div_ctl = readl(&ana_pll->sys_pll3_div_ctl);
323 /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
324 if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
327 if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
331 * When BYPASS is equal to 1, PLL enters the bypass mode
332 * regardless of the values of RESETB
334 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
337 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
338 puts("pll not locked\n");
346 case SYSTEM_PLL3_CLK:
347 case SYSTEM_PLL1_800M_CLK:
348 case SYSTEM_PLL2_1000M_CLK:
349 pll_clke_mask = INTPLL_CLKE_MASK;
353 case SYSTEM_PLL1_400M_CLK:
354 case SYSTEM_PLL2_500M_CLK:
355 pll_clke_mask = INTPLL_DIV2_CLKE_MASK;
359 case SYSTEM_PLL1_266M_CLK:
360 case SYSTEM_PLL2_333M_CLK:
361 pll_clke_mask = INTPLL_DIV3_CLKE_MASK;
365 case SYSTEM_PLL1_200M_CLK:
366 case SYSTEM_PLL2_250M_CLK:
367 pll_clke_mask = INTPLL_DIV4_CLKE_MASK;
371 case SYSTEM_PLL1_160M_CLK:
372 case SYSTEM_PLL2_200M_CLK:
373 pll_clke_mask = INTPLL_DIV5_CLKE_MASK;
377 case SYSTEM_PLL1_133M_CLK:
378 case SYSTEM_PLL2_166M_CLK:
379 pll_clke_mask = INTPLL_DIV6_CLKE_MASK;
383 case SYSTEM_PLL1_100M_CLK:
384 case SYSTEM_PLL2_125M_CLK:
385 pll_clke_mask = INTPLL_DIV8_CLKE_MASK;
389 case SYSTEM_PLL1_80M_CLK:
390 case SYSTEM_PLL2_100M_CLK:
391 pll_clke_mask = INTPLL_DIV10_CLKE_MASK;
395 case SYSTEM_PLL1_40M_CLK:
396 case SYSTEM_PLL2_50M_CLK:
397 pll_clke_mask = INTPLL_DIV20_CLKE_MASK;
404 if ((pll_gnrl_ctl & pll_clke_mask) == 0)
407 main_div = (pll_div_ctl & INTPLL_MAIN_DIV_MASK) >>
408 INTPLL_MAIN_DIV_SHIFT;
409 pre_div = (pll_div_ctl & INTPLL_PRE_DIV_MASK) >>
410 INTPLL_PRE_DIV_SHIFT;
411 post_div = (pll_div_ctl & INTPLL_POST_DIV_MASK) >>
412 INTPLL_POST_DIV_SHIFT;
414 /* FFVCO = (m * FFIN) / p, FFOUT = (m * FFIN) / (p * 2^s) */
415 freq = 24000000ULL * main_div;
416 return lldiv(freq, pre_div * (1 << post_div) * div);
419 static u32 decode_fracpll(enum clk_root_src frac_pll)
421 u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1;
422 u32 main_div, pre_div, post_div, k;
426 pll_gnrl_ctl = readl(&ana_pll->dram_pll_gnrl_ctl);
427 pll_fdiv_ctl0 = readl(&ana_pll->dram_pll_fdiv_ctl0);
428 pll_fdiv_ctl1 = readl(&ana_pll->dram_pll_fdiv_ctl1);
431 pll_gnrl_ctl = readl(&ana_pll->audio_pll1_gnrl_ctl);
432 pll_fdiv_ctl0 = readl(&ana_pll->audio_pll1_fdiv_ctl0);
433 pll_fdiv_ctl1 = readl(&ana_pll->audio_pll1_fdiv_ctl1);
436 pll_gnrl_ctl = readl(&ana_pll->audio_pll2_gnrl_ctl);
437 pll_fdiv_ctl0 = readl(&ana_pll->audio_pll2_fdiv_ctl0);
438 pll_fdiv_ctl1 = readl(&ana_pll->audio_pll2_fdiv_ctl1);
441 pll_gnrl_ctl = readl(&ana_pll->video_pll1_gnrl_ctl);
442 pll_fdiv_ctl0 = readl(&ana_pll->video_pll1_fdiv_ctl0);
443 pll_fdiv_ctl1 = readl(&ana_pll->video_pll1_fdiv_ctl1);
446 printf("Not supported\n");
450 /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
451 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0)
454 if ((pll_gnrl_ctl & RST_MASK) == 0)
457 * When BYPASS is equal to 1, PLL enters the bypass mode
458 * regardless of the values of RESETB
460 if (pll_gnrl_ctl & BYPASS_MASK)
463 if (!(pll_gnrl_ctl & LOCK_STATUS)) {
464 puts("pll not locked\n");
468 if (!(pll_gnrl_ctl & CLKE_MASK))
471 main_div = (pll_fdiv_ctl0 & MDIV_MASK) >>
473 pre_div = (pll_fdiv_ctl0 & PDIV_MASK) >>
475 post_div = (pll_fdiv_ctl0 & SDIV_MASK) >>
478 k = pll_fdiv_ctl1 & KDIV_MASK;
480 return lldiv((main_div * 65536 + k) * 24000000ULL,
481 65536 * pre_div * (1 << post_div));
484 static u32 get_root_src_clk(enum clk_root_src root_src)
496 case SYSTEM_PLL1_800M_CLK:
497 case SYSTEM_PLL1_400M_CLK:
498 case SYSTEM_PLL1_266M_CLK:
499 case SYSTEM_PLL1_200M_CLK:
500 case SYSTEM_PLL1_160M_CLK:
501 case SYSTEM_PLL1_133M_CLK:
502 case SYSTEM_PLL1_100M_CLK:
503 case SYSTEM_PLL1_80M_CLK:
504 case SYSTEM_PLL1_40M_CLK:
505 case SYSTEM_PLL2_1000M_CLK:
506 case SYSTEM_PLL2_500M_CLK:
507 case SYSTEM_PLL2_333M_CLK:
508 case SYSTEM_PLL2_250M_CLK:
509 case SYSTEM_PLL2_200M_CLK:
510 case SYSTEM_PLL2_166M_CLK:
511 case SYSTEM_PLL2_125M_CLK:
512 case SYSTEM_PLL2_100M_CLK:
513 case SYSTEM_PLL2_50M_CLK:
514 case SYSTEM_PLL3_CLK:
515 return decode_intpll(root_src);
520 return decode_fracpll(root_src);
528 static u32 get_root_clk(enum clk_root_index clock_id)
530 enum clk_root_src root_src;
531 u32 post_podf, pre_podf, root_src_clk;
533 if (clock_root_enabled(clock_id) <= 0)
536 if (clock_get_prediv(clock_id, &pre_podf) < 0)
539 if (clock_get_postdiv(clock_id, &post_podf) < 0)
542 if (clock_get_src(clock_id, &root_src) < 0)
545 root_src_clk = get_root_src_clk(root_src);
547 return root_src_clk / (post_podf + 1) / (pre_podf + 1);
550 u32 mxc_get_clock(enum mxc_clock clk)
556 return get_root_clk(ARM_A53_CLK_ROOT);
558 clock_get_target_val(IPG_CLK_ROOT, &val);
560 return get_root_clk(AHB_CLK_ROOT) / 2 / (val + 1);
562 return get_root_clk(ECSPI1_CLK_ROOT);
564 return get_root_clk(USDHC1_CLK_ROOT);
566 return get_root_clk(USDHC2_CLK_ROOT);
568 return get_root_clk(USDHC3_CLK_ROOT);
570 return get_root_clk(I2C1_CLK_ROOT);
572 return get_root_clk(UART1_CLK_ROOT);
574 return get_root_clk(QSPI_CLK_ROOT);
576 printf("Unsupported mxc_clock %d\n", clk);
583 #ifdef CONFIG_FEC_MXC
584 int set_clk_enet(enum enet_freq type)
591 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
594 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
597 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
603 /* disable the clock first */
604 clock_enable(CCGR_ENET1, 0);
605 clock_enable(CCGR_SIM_ENET, 0);
607 /* set enet axi clock 266Mhz */
608 target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
609 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
610 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
611 clock_set_target_val(ENET_AXI_CLK_ROOT, target);
613 target = CLK_ROOT_ON | enet1_ref |
614 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
615 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
616 clock_set_target_val(ENET_REF_CLK_ROOT, target);
618 target = CLK_ROOT_ON |
619 ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
620 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
621 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
622 clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
625 clock_enable(CCGR_SIM_ENET, 1);
626 clock_enable(CCGR_ENET1, 1);