2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/linkage.h>
14 #include <linux/init.h>
15 #include <asm/hardware/cache-l2x0.h>
17 .section ".text.head", "ax"
21 * The secondary kernel init calls v7_flush_dcache_all before it enables
22 * the L1; however, the L1 comes out of reset in an undefined state, so
23 * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
24 * of cache lines with uninitialized data and uninitialized tags to get
25 * written out to memory, which does really unpleasant things to the main
26 * processor. We fix this by performing an invalidate, rather than a
27 * clean + invalidate, before jumping into the kernel.
29 * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
30 * to be called for both secondary cores startup and primary core resume
31 * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S.
33 ENTRY(v7_invalidate_l1)
35 mcr p15, 2, r0, c0, c0, 0
36 mrc p15, 1, r0, c0, c0, 0
39 and r2, r1, r0, lsr #13
43 and r3, r1, r0, lsr #3 @ NumWays - 1
44 add r2, r2, #1 @ NumSets
47 add r0, r0, #4 @ SetShift
50 add r4, r3, #1 @ NumWays
51 1: sub r2, r2, #1 @ NumSets--
52 mov r3, r4 @ Temp = NumWays
53 2: subs r3, r3, #1 @ Temp--
56 orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
57 mcr p15, 0, r5, c7, c6, 2
64 ENDPROC(v7_invalidate_l1)
67 ENTRY(v7_secondary_startup)
70 ENDPROC(v7_secondary_startup)