2 * Copyright 2011-2013 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
14 #include <linux/irq.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/irqchip/arm-gic.h>
21 #define GPC_IMR1 0x008
22 #define GPC_PGC_CPU_PDN 0x2a0
23 #define GPC_PGC_CPU_PUPSCR 0x2a4
24 #define GPC_PGC_CPU_PDNSCR 0x2a8
25 #define GPC_PGC_SW2ISO_SHIFT 0x8
26 #define GPC_PGC_SW_SHIFT 0x0
30 static void __iomem *gpc_base;
31 static u32 gpc_wake_irqs[IMR_NUM];
32 static u32 gpc_saved_imrs[IMR_NUM];
34 void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw)
36 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
37 (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR);
40 void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw)
42 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
43 (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR);
46 void imx_gpc_set_arm_power_in_lpm(bool power_off)
48 writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);
51 void imx_gpc_pre_suspend(bool arm_power_off)
53 void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
56 /* Tell GPC to power off ARM core when suspend */
58 imx_gpc_set_arm_power_in_lpm(arm_power_off);
60 for (i = 0; i < IMR_NUM; i++) {
61 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
62 writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
66 void imx_gpc_post_resume(void)
68 void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
71 /* Keep ARM core powered on for other low-power modes */
72 imx_gpc_set_arm_power_in_lpm(false);
74 for (i = 0; i < IMR_NUM; i++)
75 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
78 static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
80 unsigned int idx = d->hwirq / 32 - 1;
83 /* Sanity check for SPI irq */
87 mask = 1 << d->hwirq % 32;
88 gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
89 gpc_wake_irqs[idx] & ~mask;
94 void imx_gpc_mask_all(void)
96 void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
99 for (i = 0; i < IMR_NUM; i++) {
100 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
101 writel_relaxed(~0, reg_imr1 + i * 4);
106 void imx_gpc_restore_all(void)
108 void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
111 for (i = 0; i < IMR_NUM; i++)
112 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
115 void imx_gpc_hwirq_unmask(unsigned int hwirq)
120 reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
121 val = readl_relaxed(reg);
122 val &= ~(1 << hwirq % 32);
123 writel_relaxed(val, reg);
126 void imx_gpc_hwirq_mask(unsigned int hwirq)
131 reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
132 val = readl_relaxed(reg);
133 val |= 1 << (hwirq % 32);
134 writel_relaxed(val, reg);
137 static void imx_gpc_irq_unmask(struct irq_data *d)
139 /* Sanity check for SPI irq */
143 imx_gpc_hwirq_unmask(d->hwirq);
146 static void imx_gpc_irq_mask(struct irq_data *d)
148 /* Sanity check for SPI irq */
152 imx_gpc_hwirq_mask(d->hwirq);
155 void __init imx_gpc_init(void)
157 struct device_node *np;
160 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
161 gpc_base = of_iomap(np, 0);
164 /* Initially mask all interrupts */
165 for (i = 0; i < IMR_NUM; i++)
166 writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
168 /* Register GPC as the secondary interrupt controller behind GIC */
169 gic_arch_extn.irq_mask = imx_gpc_irq_mask;
170 gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
171 gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;