2 * Author: MontaVista Software, Inc.
5 * Based on the OMAP devices.c
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
14 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
15 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
16 * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version 2
21 * of the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/init.h>
35 #include <linux/platform_device.h>
36 #include <linux/gpio.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/serial.h>
40 #include <mach/irqs.h>
41 #include <mach/hardware.h>
42 #include <mach/common.h>
47 #if defined(CONFIG_ARCH_MX1)
48 /* GPIO port description */
49 static struct mxc_gpio_port imx_gpio_ports[] = {
51 .chip.label = "gpio-0",
52 .base = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
53 .irq = MX1_GPIO_INT_PORTA,
54 .virtual_irq_start = MXC_GPIO_IRQ_START,
56 .chip.label = "gpio-1",
57 .base = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
58 .irq = MX1_GPIO_INT_PORTB,
59 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
61 .chip.label = "gpio-2",
62 .base = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
63 .irq = MX1_GPIO_INT_PORTC,
64 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
66 .chip.label = "gpio-3",
67 .base = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
68 .irq = MX1_GPIO_INT_PORTD,
69 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
73 int __init imx1_register_gpios(void)
75 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
79 #if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
82 * - i.MX1: the basic controller
83 * - i.MX21: to be checked
84 * - i.MX27: like i.MX1, with slightly variations
86 static struct resource mxc_fb[] = {
88 .start = MX2x_LCDC_BASE_ADDR,
89 .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
90 .flags = IORESOURCE_MEM,
92 .start = MX2x_INT_LCDC,
94 .flags = IORESOURCE_IRQ,
99 struct platform_device mxc_fb_device = {
102 .num_resources = ARRAY_SIZE(mxc_fb),
105 .coherent_dma_mask = DMA_BIT_MASK(32),
109 static struct resource mxc_pwm_resources[] = {
111 .start = MX2x_PWM_BASE_ADDR,
112 .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
113 .flags = IORESOURCE_MEM,
115 .start = MX2x_INT_PWM,
117 .flags = IORESOURCE_IRQ,
121 struct platform_device mxc_pwm_device = {
124 .num_resources = ARRAY_SIZE(mxc_pwm_resources),
125 .resource = mxc_pwm_resources,
128 #define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
129 static struct resource mxc_sdhc_resources ## n[] = { \
132 .end = baseaddr + SZ_4K - 1, \
133 .flags = IORESOURCE_MEM, \
137 .flags = IORESOURCE_IRQ, \
141 .flags = IORESOURCE_DMA, \
145 static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
147 struct platform_device mxc_sdhc_device ## n = { \
151 .dma_mask = &mxc_sdhc ## n ## _dmamask, \
152 .coherent_dma_mask = DMA_BIT_MASK(32), \
154 .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
155 .resource = mxc_sdhc_resources ## n, \
158 DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
159 DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
161 #ifdef CONFIG_MACH_MX27
162 static struct resource otg_resources[] = {
164 .start = MX27_USBOTG_BASE_ADDR,
165 .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
166 .flags = IORESOURCE_MEM,
168 .start = MX27_INT_USB3,
169 .end = MX27_INT_USB3,
170 .flags = IORESOURCE_IRQ,
174 static u64 otg_dmamask = DMA_BIT_MASK(32);
176 /* OTG gadget device */
177 struct platform_device mxc_otg_udc_device = {
178 .name = "fsl-usb2-udc",
181 .dma_mask = &otg_dmamask,
182 .coherent_dma_mask = DMA_BIT_MASK(32),
184 .resource = otg_resources,
185 .num_resources = ARRAY_SIZE(otg_resources),
189 struct platform_device mxc_otg_host = {
193 .coherent_dma_mask = DMA_BIT_MASK(32),
194 .dma_mask = &otg_dmamask,
196 .resource = otg_resources,
197 .num_resources = ARRAY_SIZE(otg_resources),
202 static u64 usbh1_dmamask = DMA_BIT_MASK(32);
204 static struct resource mxc_usbh1_resources[] = {
206 .start = MX27_USBOTG_BASE_ADDR + 0x200,
207 .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
208 .flags = IORESOURCE_MEM,
210 .start = MX27_INT_USB1,
211 .end = MX27_INT_USB1,
212 .flags = IORESOURCE_IRQ,
216 struct platform_device mxc_usbh1 = {
220 .coherent_dma_mask = DMA_BIT_MASK(32),
221 .dma_mask = &usbh1_dmamask,
223 .resource = mxc_usbh1_resources,
224 .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
228 static u64 usbh2_dmamask = DMA_BIT_MASK(32);
230 static struct resource mxc_usbh2_resources[] = {
232 .start = MX27_USBOTG_BASE_ADDR + 0x400,
233 .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
234 .flags = IORESOURCE_MEM,
236 .start = MX27_INT_USB2,
237 .end = MX27_INT_USB2,
238 .flags = IORESOURCE_IRQ,
242 struct platform_device mxc_usbh2 = {
246 .coherent_dma_mask = DMA_BIT_MASK(32),
247 .dma_mask = &usbh2_dmamask,
249 .resource = mxc_usbh2_resources,
250 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
254 /* GPIO port description */
255 #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
257 .chip.label = "gpio-" #n, \
259 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
261 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
264 #define DEFINE_MXC_GPIO_PORT(SOC, n) \
266 .chip.label = "gpio-" #n, \
267 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
269 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
272 #define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
273 static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
274 DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
275 DEFINE_MXC_GPIO_PORT(SOC, 1), \
276 DEFINE_MXC_GPIO_PORT(SOC, 2), \
277 DEFINE_MXC_GPIO_PORT(SOC, 3), \
278 DEFINE_MXC_GPIO_PORT(SOC, 4), \
279 DEFINE_MXC_GPIO_PORT(SOC, 5), \
282 #ifdef CONFIG_MACH_MX21
283 DEFINE_MXC_GPIO_PORTS(MX21, imx21);
285 int __init imx21_register_gpios(void)
287 return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
291 #ifdef CONFIG_MACH_MX27
292 DEFINE_MXC_GPIO_PORTS(MX27, imx27);
294 int __init imx27_register_gpios(void)
296 return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
300 #ifdef CONFIG_MACH_MX21
301 static struct resource mx21_usbhc_resources[] = {
303 .start = MX21_USBOTG_BASE_ADDR,
304 .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
305 .flags = IORESOURCE_MEM,
308 .start = MX21_INT_USBHOST,
309 .end = MX21_INT_USBHOST,
310 .flags = IORESOURCE_IRQ,
314 struct platform_device mx21_usbhc_device = {
318 .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
319 .coherent_dma_mask = DMA_BIT_MASK(32),
321 .num_resources = ARRAY_SIZE(mx21_usbhc_resources),
322 .resource = mx21_usbhc_resources,
326 static struct resource imx_kpp_resources[] = {
328 .start = MX2x_KPP_BASE_ADDR,
329 .end = MX2x_KPP_BASE_ADDR + 0xf,
330 .flags = IORESOURCE_MEM
332 .start = MX2x_INT_KPP,
334 .flags = IORESOURCE_IRQ,
338 struct platform_device imx_kpp_device = {
339 .name = "imx-keypad",
341 .num_resources = ARRAY_SIZE(imx_kpp_resources),
342 .resource = imx_kpp_resources,