2 * Author: MontaVista Software, Inc.
5 * Based on the OMAP devices.c
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
14 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
15 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
16 * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version 2
21 * of the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/init.h>
35 #include <linux/platform_device.h>
36 #include <linux/gpio.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/serial.h>
40 #include <mach/irqs.h>
41 #include <mach/hardware.h>
42 #include <mach/common.h>
47 #if defined(CONFIG_ARCH_MX1)
48 static struct resource imx1_camera_resources[] = {
52 .flags = IORESOURCE_MEM,
56 .flags = IORESOURCE_IRQ,
60 static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
62 struct platform_device imx1_camera_device = {
64 .id = 0, /* This is used to put cameras on this interface */
66 .dma_mask = &imx1_camera_dmamask,
67 .coherent_dma_mask = DMA_BIT_MASK(32),
69 .resource = imx1_camera_resources,
70 .num_resources = ARRAY_SIZE(imx1_camera_resources),
73 static struct resource imx_rtc_resources[] = {
77 .flags = IORESOURCE_MEM,
81 .flags = IORESOURCE_IRQ,
83 .start = MX1_RTC_SAMINT,
84 .end = MX1_RTC_SAMINT,
85 .flags = IORESOURCE_IRQ,
89 struct platform_device imx_rtc_device = {
92 .resource = imx_rtc_resources,
93 .num_resources = ARRAY_SIZE(imx_rtc_resources),
96 static struct resource imx_wdt_resources[] = {
100 .flags = IORESOURCE_MEM,
102 .start = MX1_WDT_INT,
104 .flags = IORESOURCE_IRQ,
108 struct platform_device imx_wdt_device = {
111 .resource = imx_wdt_resources,
112 .num_resources = ARRAY_SIZE(imx_wdt_resources),
115 static struct resource imx_usb_resources[] = {
119 .flags = IORESOURCE_MEM,
121 .start = MX1_USBD_INT0,
122 .end = MX1_USBD_INT0,
123 .flags = IORESOURCE_IRQ,
125 .start = MX1_USBD_INT1,
126 .end = MX1_USBD_INT1,
127 .flags = IORESOURCE_IRQ,
129 .start = MX1_USBD_INT2,
130 .end = MX1_USBD_INT2,
131 .flags = IORESOURCE_IRQ,
133 .start = MX1_USBD_INT3,
134 .end = MX1_USBD_INT3,
135 .flags = IORESOURCE_IRQ,
137 .start = MX1_USBD_INT4,
138 .end = MX1_USBD_INT4,
139 .flags = IORESOURCE_IRQ,
141 .start = MX1_USBD_INT5,
142 .end = MX1_USBD_INT5,
143 .flags = IORESOURCE_IRQ,
145 .start = MX1_USBD_INT6,
146 .end = MX1_USBD_INT6,
147 .flags = IORESOURCE_IRQ,
151 struct platform_device imx_usb_device = {
154 .num_resources = ARRAY_SIZE(imx_usb_resources),
155 .resource = imx_usb_resources,
158 /* GPIO port description */
159 static struct mxc_gpio_port imx_gpio_ports[] = {
161 .chip.label = "gpio-0",
162 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
163 .irq = MX1_GPIO_INT_PORTA,
164 .virtual_irq_start = MXC_GPIO_IRQ_START,
166 .chip.label = "gpio-1",
167 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
168 .irq = MX1_GPIO_INT_PORTB,
169 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
171 .chip.label = "gpio-2",
172 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
173 .irq = MX1_GPIO_INT_PORTC,
174 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
176 .chip.label = "gpio-3",
177 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
178 .irq = MX1_GPIO_INT_PORTD,
179 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
183 int __init imx1_register_gpios(void)
185 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
189 #if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
191 #ifdef CONFIG_MACH_MX27
192 static struct resource mx27_camera_resources[] = {
194 .start = MX27_CSI_BASE_ADDR,
195 .end = MX27_CSI_BASE_ADDR + 0x1f,
196 .flags = IORESOURCE_MEM,
198 .start = MX27_EMMA_PRP_BASE_ADDR,
199 .end = MX27_EMMA_PRP_BASE_ADDR + 0x1f,
200 .flags = IORESOURCE_MEM,
202 .start = MX27_INT_CSI,
204 .flags = IORESOURCE_IRQ,
206 .start = MX27_INT_EMMAPRP,
207 .end = MX27_INT_EMMAPRP,
208 .flags = IORESOURCE_IRQ,
211 struct platform_device mx27_camera_device = {
212 .name = "mx2-camera",
214 .num_resources = ARRAY_SIZE(mx27_camera_resources),
215 .resource = mx27_camera_resources,
217 .coherent_dma_mask = 0xffffffff,
223 * General Purpose Timer
227 #define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
228 static struct resource timer ## n ##_resources[] = { \
231 .end = baseaddr + SZ_4K - 1, \
232 .flags = IORESOURCE_MEM, \
236 .flags = IORESOURCE_IRQ, \
240 struct platform_device mxc_gpt ## n = { \
243 .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
244 .resource = timer ## n ## _resources, \
247 /* We use gpt1 as system timer, so do not add a device for this one */
248 DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
249 DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
251 #ifdef CONFIG_MACH_MX27
252 DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
253 DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
254 DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
257 /* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
258 static struct resource mxc_wdt_resources[] = {
260 .start = MX2x_WDOG_BASE_ADDR,
261 .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
262 .flags = IORESOURCE_MEM,
266 struct platform_device mxc_wdt = {
269 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
270 .resource = mxc_wdt_resources,
273 static struct resource mxc_w1_master_resources[] = {
275 .start = MX2x_OWIRE_BASE_ADDR,
276 .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
277 .flags = IORESOURCE_MEM,
281 struct platform_device mxc_w1_master_device = {
284 .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
285 .resource = mxc_w1_master_resources,
290 * - i.MX1: the basic controller
291 * - i.MX21: to be checked
292 * - i.MX27: like i.MX1, with slightly variations
294 static struct resource mxc_fb[] = {
296 .start = MX2x_LCDC_BASE_ADDR,
297 .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
298 .flags = IORESOURCE_MEM,
300 .start = MX2x_INT_LCDC,
301 .end = MX2x_INT_LCDC,
302 .flags = IORESOURCE_IRQ,
307 struct platform_device mxc_fb_device = {
310 .num_resources = ARRAY_SIZE(mxc_fb),
313 .coherent_dma_mask = DMA_BIT_MASK(32),
317 #ifdef CONFIG_MACH_MX27
318 static struct resource mxc_fec_resources[] = {
320 .start = MX27_FEC_BASE_ADDR,
321 .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
322 .flags = IORESOURCE_MEM,
324 .start = MX27_INT_FEC,
326 .flags = IORESOURCE_IRQ,
330 struct platform_device mxc_fec_device = {
333 .num_resources = ARRAY_SIZE(mxc_fec_resources),
334 .resource = mxc_fec_resources,
338 static struct resource mxc_pwm_resources[] = {
340 .start = MX2x_PWM_BASE_ADDR,
341 .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
342 .flags = IORESOURCE_MEM,
344 .start = MX2x_INT_PWM,
346 .flags = IORESOURCE_IRQ,
350 struct platform_device mxc_pwm_device = {
353 .num_resources = ARRAY_SIZE(mxc_pwm_resources),
354 .resource = mxc_pwm_resources,
357 #define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
358 static struct resource mxc_sdhc_resources ## n[] = { \
361 .end = baseaddr + SZ_4K - 1, \
362 .flags = IORESOURCE_MEM, \
366 .flags = IORESOURCE_IRQ, \
370 .flags = IORESOURCE_DMA, \
374 static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
376 struct platform_device mxc_sdhc_device ## n = { \
380 .dma_mask = &mxc_sdhc ## n ## _dmamask, \
381 .coherent_dma_mask = DMA_BIT_MASK(32), \
383 .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
384 .resource = mxc_sdhc_resources ## n, \
387 DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
388 DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
390 #ifdef CONFIG_MACH_MX27
391 static struct resource otg_resources[] = {
393 .start = MX27_USBOTG_BASE_ADDR,
394 .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
395 .flags = IORESOURCE_MEM,
397 .start = MX27_INT_USB3,
398 .end = MX27_INT_USB3,
399 .flags = IORESOURCE_IRQ,
403 static u64 otg_dmamask = DMA_BIT_MASK(32);
405 /* OTG gadget device */
406 struct platform_device mxc_otg_udc_device = {
407 .name = "fsl-usb2-udc",
410 .dma_mask = &otg_dmamask,
411 .coherent_dma_mask = DMA_BIT_MASK(32),
413 .resource = otg_resources,
414 .num_resources = ARRAY_SIZE(otg_resources),
418 struct platform_device mxc_otg_host = {
422 .coherent_dma_mask = DMA_BIT_MASK(32),
423 .dma_mask = &otg_dmamask,
425 .resource = otg_resources,
426 .num_resources = ARRAY_SIZE(otg_resources),
431 static u64 usbh1_dmamask = DMA_BIT_MASK(32);
433 static struct resource mxc_usbh1_resources[] = {
435 .start = MX27_USBOTG_BASE_ADDR + 0x200,
436 .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
437 .flags = IORESOURCE_MEM,
439 .start = MX27_INT_USB1,
440 .end = MX27_INT_USB1,
441 .flags = IORESOURCE_IRQ,
445 struct platform_device mxc_usbh1 = {
449 .coherent_dma_mask = DMA_BIT_MASK(32),
450 .dma_mask = &usbh1_dmamask,
452 .resource = mxc_usbh1_resources,
453 .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
457 static u64 usbh2_dmamask = DMA_BIT_MASK(32);
459 static struct resource mxc_usbh2_resources[] = {
461 .start = MX27_USBOTG_BASE_ADDR + 0x400,
462 .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
463 .flags = IORESOURCE_MEM,
465 .start = MX27_INT_USB2,
466 .end = MX27_INT_USB2,
467 .flags = IORESOURCE_IRQ,
471 struct platform_device mxc_usbh2 = {
475 .coherent_dma_mask = DMA_BIT_MASK(32),
476 .dma_mask = &usbh2_dmamask,
478 .resource = mxc_usbh2_resources,
479 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
483 #define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
486 .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
487 .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
488 .flags = IORESOURCE_DMA, \
491 #define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
492 static struct resource imx_ssi_resources ## n[] = { \
494 .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
495 .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
496 .flags = IORESOURCE_MEM, \
498 .start = MX2x_INT_SSI1, \
499 .end = MX2x_INT_SSI1, \
500 .flags = IORESOURCE_IRQ, \
502 DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
503 DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
504 DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
505 DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
508 struct platform_device imx_ssi_device ## n = { \
511 .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
512 .resource = imx_ssi_resources ## n, \
515 DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
516 DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
518 /* GPIO port description */
519 #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
521 .chip.label = "gpio-" #n, \
523 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
525 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
528 #define DEFINE_MXC_GPIO_PORT(SOC, n) \
530 .chip.label = "gpio-" #n, \
531 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
533 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
536 #define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
537 static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
538 DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
539 DEFINE_MXC_GPIO_PORT(SOC, 1), \
540 DEFINE_MXC_GPIO_PORT(SOC, 2), \
541 DEFINE_MXC_GPIO_PORT(SOC, 3), \
542 DEFINE_MXC_GPIO_PORT(SOC, 4), \
543 DEFINE_MXC_GPIO_PORT(SOC, 5), \
546 #ifdef CONFIG_MACH_MX21
547 DEFINE_MXC_GPIO_PORTS(MX21, imx21);
549 int __init imx21_register_gpios(void)
551 return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
555 #ifdef CONFIG_MACH_MX27
556 DEFINE_MXC_GPIO_PORTS(MX27, imx27);
558 int __init imx27_register_gpios(void)
560 return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
564 #ifdef CONFIG_MACH_MX21
565 static struct resource mx21_usbhc_resources[] = {
567 .start = MX21_USBOTG_BASE_ADDR,
568 .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
569 .flags = IORESOURCE_MEM,
572 .start = MX21_INT_USBHOST,
573 .end = MX21_INT_USBHOST,
574 .flags = IORESOURCE_IRQ,
578 struct platform_device mx21_usbhc_device = {
582 .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
583 .coherent_dma_mask = DMA_BIT_MASK(32),
585 .num_resources = ARRAY_SIZE(mx21_usbhc_resources),
586 .resource = mx21_usbhc_resources,
590 static struct resource imx_kpp_resources[] = {
592 .start = MX2x_KPP_BASE_ADDR,
593 .end = MX2x_KPP_BASE_ADDR + 0xf,
594 .flags = IORESOURCE_MEM
596 .start = MX2x_INT_KPP,
598 .flags = IORESOURCE_IRQ,
602 struct platform_device imx_kpp_device = {
603 .name = "imx-keypad",
605 .num_resources = ARRAY_SIZE(imx_kpp_resources),
606 .resource = imx_kpp_resources,