arch/arm/mach-imx/clk-imx51-imx53.c

   1 /*
   2  * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  */
   9 #include <linux/mm.h>
  10 #include <linux/delay.h>
  11 #include <linux/clk.h>
  12 #include <linux/io.h>
  13 #include <linux/clkdev.h>
  14 #include <linux/of.h>
  15 #include <linux/err.h>
  16
  17 #include "crm-regs-imx5.h"
  18 #include "clk.h"
  19 #include "common.h"
  20 #include "hardware.h"
  21
  22 /* Low-power Audio Playback Mode clock */
  23 static const char *lp_apm_sel[] = { "osc", };
  24
  25 /* This is used multiple times */
  26 static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", };
  27 static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", };
  28 static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", };
  29 static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", };
  30 static const char *per_root_sel[] = { "per_podf", "ipg", };
  31 static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
  32 static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
  33 static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", };
  34 static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", };
  35 static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", };
  36 static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", };
  37 static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
  38 static const char *emi_slow_sel[] = { "main_bus", "ahb", };
  39 static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
  40 static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
  41 static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
  42 static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
  43 static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
  44 static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
  45 static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
  46 static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
  47 static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
  48 static const char *mx51_tve_sel[] = { "tve_pred", "tve_ext_sel", };
  49 static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
  50 static const char *gpu3d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
  51 static const char *gpu2d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
  52 static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
  53 static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
  54 static const char *mx53_cko1_sel[] = {
  55         "cpu_podf", "pll1_sw", "pll2_sw", "pll3_sw",
  56         "emi_slow_podf", "pll4_sw", "nfc_podf", "dummy",
  57         "di_pred", "dummy", "dummy", "ahb",
  58         "ipg", "per_root", "ckil", "dummy",};
  59 static const char *mx53_cko2_sel[] = {
  60         "dummy"/* dptc_core */, "dummy"/* dptc_perich */,
  61         "dummy", "esdhc_a_podf",
  62         "usboh3_podf", "dummy"/* wrck_clk_root */,
  63         "ecspi_podf", "dummy"/* pll1_ref_clk */,
  64         "esdhc_b_podf", "dummy"/* ddr_clk_root */,
  65         "dummy"/* arm_axi_clk_root */, "dummy"/* usb_phy_out */,
  66         "vpu_sel", "ipu_sel",
  67         "osc", "ckih1",
  68         "dummy", "esdhc_c_sel",
  69         "ssi1_root_podf", "ssi2_root_podf",
  70         "dummy", "dummy",
  71         "dummy"/* lpsr_clk_root */, "dummy"/* pgc_clk_root */,
  72         "dummy"/* tve_out */, "usb_phy_sel",
  73         "tve_sel", "lp_apm",
  74         "uart_root", "dummy"/* spdif0_clk_root */,
  75         "dummy", "dummy", };
  76
  77 enum imx5_clks {
  78         dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
  79         uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s,
  80         emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred,
  81         usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di_unused,
  82         tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,
  83         uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,
  84         gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate,
  85         gpt_hf_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
  86         esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate,
  87         ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate,
  88         ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s,
  89         ipu_gate, nfc_gate, ipu_di1_gate, vpu_s, vpu_gate,
  90         vpu_reference_gate, uart4_ipg_gate, uart4_per_gate, uart5_ipg_gate,
  91         uart5_per_gate, tve_gate, tve_pred, esdhc1_per_gate, esdhc2_per_gate,
  92         esdhc3_per_gate, esdhc4_per_gate, usb_phy_gate, hsi2c_gate,
  93         mipi_hsc1_gate, mipi_hsc2_gate, mipi_esc_gate, mipi_hsp_gate,
  94         ldb_di1_div_3_5, ldb_di1_div, ldb_di0_div_3_5, ldb_di0_div,
  95         ldb_di1_gate, can2_serial_gate, can2_ipg_gate, i2c3_gate, lp_apm,
  96         periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2,
  97         tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf,
  98         esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel, iim_gate,
  99         usboh3_gate, emi_fast_gate, ipu_di0_gate,gpc_dvfs, pll1_sw, pll2_sw,
 100         pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw,
 101         ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate,
 102         usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root,
 103         ssi_apm, ssi1_root_sel, ssi2_root_sel, ssi3_root_sel, ssi_ext1_sel,
 104         ssi_ext2_sel, ssi_ext1_com_sel, ssi_ext2_com_sel, ssi1_root_pred,
 105         ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred,
 106         ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
 107         ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
 108         epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
 109         can_sel, can1_serial_gate, can1_ipg_gate,
 110         owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate,
 111         cko1_sel, cko1_podf, cko1,
 112         cko2_sel, cko2_podf, cko2,
 113         srtc_gate, pata_gate,
 114         clk_max
 115 };
 116
 117 static struct clk *clk[clk_max];
 118 static struct clk_onecell_data clk_data;
 119
 120 static void __init mx5_clocks_common_init(unsigned long rate_ckil,
 121                 unsigned long rate_osc, unsigned long rate_ckih1,
 122                 unsigned long rate_ckih2)
 123 {
 124         int i;
 125
 126         clk[dummy] = imx_clk_fixed("dummy", 0);
 127         clk[ckil] = imx_clk_fixed("ckil", rate_ckil);
 128         clk[osc] = imx_clk_fixed("osc", rate_osc);
 129         clk[ckih1] = imx_clk_fixed("ckih1", rate_ckih1);
 130         clk[ckih2] = imx_clk_fixed("ckih2", rate_ckih2);
 131
 132         clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
 133                                 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
 134         clk[periph_apm] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
 135                                 periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
 136         clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
 137                                 main_bus_sel, ARRAY_SIZE(main_bus_sel));
 138         clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
 139                                 per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
 140         clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
 141         clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
 142         clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
 143         clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
 144                                 per_root_sel, ARRAY_SIZE(per_root_sel));
 145         clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
 146         clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
 147         clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
 148         clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
 149         clk[tmax1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
 150         clk[tmax2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
 151         clk[tmax3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
 152         clk[spba] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
 153         clk[ipg] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
 154         clk[axi_a] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
 155         clk[axi_b] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
 156         clk[uart_sel] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
 157                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 158         clk[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
 159         clk[uart_root] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
 160
 161         clk[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
 162                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 163         clk[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
 164                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 165         clk[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
 166         clk[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
 167         clk[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
 168         clk[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
 169         clk[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
 170         clk[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
 171
 172         clk[emi_sel] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
 173                                 emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
 174         clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
 175         clk[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
 176         clk[ecspi_sel] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
 177                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 178         clk[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
 179         clk[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
 180         clk[usboh3_sel] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
 181                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 182         clk[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
 183         clk[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
 184         clk[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
 185         clk[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
 186         clk[usb_phy_sel] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
 187                                 usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
 188         clk[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
 189         clk[di_pred] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
 190         clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
 191         clk[uart1_ipg_gate] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
 192         clk[uart1_per_gate] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
 193         clk[uart2_ipg_gate] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
 194         clk[uart2_per_gate] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
 195         clk[uart3_ipg_gate] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
 196         clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
 197         clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
 198         clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
 199         clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
 200         clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
 201         clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
 202         clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
 203         clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
 204         clk[gpt_hf_gate] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
 205         clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
 206         clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
 207         clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
 208         clk[esdhc1_ipg_gate] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
 209         clk[esdhc2_ipg_gate] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
 210         clk[esdhc3_ipg_gate] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
 211         clk[esdhc4_ipg_gate] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
 212         clk[ssi1_ipg_gate] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
 213         clk[ssi2_ipg_gate] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
 214         clk[ssi3_ipg_gate] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
 215         clk[ecspi1_ipg_gate] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
 216         clk[ecspi1_per_gate] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
 217         clk[ecspi2_ipg_gate] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
 218         clk[ecspi2_per_gate] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
 219         clk[cspi_ipg_gate] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
 220         clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
 221         clk[emi_fast_gate] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
 222         clk[emi_slow_gate] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
 223         clk[ipu_s] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
 224         clk[ipu_gate] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
 225         clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
 226         clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
 227         clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
 228         clk[gpu3d_s] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel));
 229         clk[gpu2d_s] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel));
 230         clk[gpu3d_gate] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2);
 231         clk[garb_gate] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4);
 232         clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14);
 233         clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
 234         clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
 235         clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
 236         clk[uart4_ipg_gate] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
 237         clk[uart4_per_gate] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
 238         clk[uart5_ipg_gate] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
 239         clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
 240         clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
 241
 242         clk[ssi_apm] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
 243         clk[ssi1_root_sel] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
 244         clk[ssi2_root_sel] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
 245         clk[ssi3_root_sel] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
 246         clk[ssi_ext1_sel] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
 247         clk[ssi_ext2_sel] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
 248         clk[ssi_ext1_com_sel] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
 249         clk[ssi_ext2_com_sel] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
 250         clk[ssi1_root_pred] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
 251         clk[ssi1_root_podf] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
 252         clk[ssi2_root_pred] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
 253         clk[ssi2_root_podf] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
 254         clk[ssi_ext1_pred] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
 255         clk[ssi_ext1_podf] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
 256         clk[ssi_ext2_pred] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
 257         clk[ssi_ext2_podf] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
 258         clk[ssi1_root_gate] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
 259         clk[ssi2_root_gate] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
 260         clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
 261         clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
 262         clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
 263         clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
 264         clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
 265         clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
 266         clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
 267         clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
 268         clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
 269         clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
 270
 271         for (i = 0; i < ARRAY_SIZE(clk); i++)
 272                 if (IS_ERR(clk[i]))
 273                         pr_err("i.MX5 clk %d: register failed with %ld\n",
 274                                 i, PTR_ERR(clk[i]));
 275
 276         clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0");
 277         clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
 278         clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
 279         clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
 280         clk_register_clkdev(clk[uart2_per_gate], "per", "imx21-uart.1");
 281         clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
 282         clk_register_clkdev(clk[uart3_per_gate], "per", "imx21-uart.2");
 283         clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
 284         clk_register_clkdev(clk[uart4_per_gate], "per", "imx21-uart.3");
 285         clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
 286         clk_register_clkdev(clk[uart5_per_gate], "per", "imx21-uart.4");
 287         clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
 288         clk_register_clkdev(clk[ecspi1_per_gate], "per", "imx51-ecspi.0");
 289         clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0");
 290         clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1");
 291         clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1");
 292         clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2");
 293         clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0");
 294         clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
 295         clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
 296         clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
 297         clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0");
 298         clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0");
 299         clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0");
 300         clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1");
 301         clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1");
 302         clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1");
 303         clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2");
 304         clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2");
 305         clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2");
 306         clk_register_clkdev(clk[usboh3_per_gate], "per", "imx-udc-mx51");
 307         clk_register_clkdev(clk[usboh3_gate], "ipg", "imx-udc-mx51");
 308         clk_register_clkdev(clk[usboh3_gate], "ahb", "imx-udc-mx51");
 309         clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand");
 310         clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
 311         clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
 312         clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
 313         clk_register_clkdev(clk[ssi_ext1_gate], "ssi_ext1", NULL);
 314         clk_register_clkdev(clk[ssi_ext2_gate], "ssi_ext2", NULL);
 315         clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
 316         clk_register_clkdev(clk[cpu_podf], NULL, "cpufreq-cpu0.0");
 317         clk_register_clkdev(clk[iim_gate], "iim", NULL);
 318         clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
 319         clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
 320         clk_register_clkdev(clk[dummy], NULL, "imx-keypad");
 321         clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
 322         clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
 323         clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0");
 324         clk_register_clkdev(clk[epit1_hf_gate], "per", "imx-epit.0");
 325         clk_register_clkdev(clk[epit2_ipg_gate], "ipg", "imx-epit.1");
 326         clk_register_clkdev(clk[epit2_hf_gate], "per", "imx-epit.1");
 327
 328         /* Set SDHC parents to be PLL2 */
 329         clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
 330         clk_set_parent(clk[esdhc_b_sel], clk[pll2_sw]);
 331
 332         /* move usb phy clk to 24MHz */
 333         clk_set_parent(clk[usb_phy_sel], clk[osc]);
 334
 335         clk_prepare_enable(clk[gpc_dvfs]);
 336         clk_prepare_enable(clk[ahb_max]); /* esdhc3 */
 337         clk_prepare_enable(clk[aips_tz1]);
 338         clk_prepare_enable(clk[aips_tz2]); /* fec */
 339         clk_prepare_enable(clk[spba]);
 340         clk_prepare_enable(clk[emi_fast_gate]); /* fec */
 341         clk_prepare_enable(clk[emi_slow_gate]); /* eim */
 342         clk_prepare_enable(clk[mipi_hsc1_gate]);
 343         clk_prepare_enable(clk[mipi_hsc2_gate]);
 344         clk_prepare_enable(clk[mipi_esc_gate]);
 345         clk_prepare_enable(clk[mipi_hsp_gate]);
 346         clk_prepare_enable(clk[tmax1]);
 347         clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
 348         clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
 349 }
 350
 351 int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 352                         unsigned long rate_ckih1, unsigned long rate_ckih2)
 353 {
 354         int i;
 355         u32 val;
 356         struct device_node *np;
 357
 358         clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
 359         clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
 360         clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
 361         clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
 362                                 mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
 363         clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
 364                                 mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
 365         clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
 366                                 mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT);
 367         clk[tve_s] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1,
 368                                 mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
 369         clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
 370         clk[tve_pred] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
 371         clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
 372         clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
 373         clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
 374         clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
 375         clk[usb_phy_gate] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
 376         clk[hsi2c_gate] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
 377         clk[mipi_hsc1_gate] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
 378         clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
 379         clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
 380         clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
 381
 382         for (i = 0; i < ARRAY_SIZE(clk); i++)
 383                 if (IS_ERR(clk[i]))
 384                         pr_err("i.MX51 clk %d: register failed with %ld\n",
 385                                 i, PTR_ERR(clk[i]));
 386
 387         np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm");
 388         clk_data.clks = clk;
 389         clk_data.clk_num = ARRAY_SIZE(clk);
 390         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 391
 392         mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
 393
 394         clk_register_clkdev(clk[hsi2c_gate], NULL, "imx21-i2c.2");
 395         clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
 396         clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
 397         clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
 398         clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
 399         clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
 400         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
 401         clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx51.0");
 402         clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx51.1");
 403         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.1");
 404         clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx51.1");
 405         clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx51.2");
 406         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.2");
 407         clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx51.2");
 408         clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
 409         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
 410         clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
 411
 412         /* set the usboh3 parent to pll2_sw */
 413         clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
 414
 415         /* set SDHC root clock to 166.25MHZ*/
 416         clk_set_rate(clk[esdhc_a_podf], 166250000);
 417         clk_set_rate(clk[esdhc_b_podf], 166250000);
 418
 419         /* System timer */
 420         mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
 421
 422         clk_prepare_enable(clk[iim_gate]);
 423         imx_print_silicon_rev("i.MX51", mx51_revision());
 424         clk_disable_unprepare(clk[iim_gate]);
 425
 426         /*
 427          * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
 428          * longer supported. Set to one for better power saving.
 429          *
 430          * The effect of not setting these bits is that MIPI clocks can't be
 431          * enabled without the IPU clock being enabled aswell.
 432          */
 433         val = readl(MXC_CCM_CCDR);
 434         val |= 1 << 18;
 435         writel(val, MXC_CCM_CCDR);
 436
 437         val = readl(MXC_CCM_CLPCR);
 438         val |= 1 << 23;
 439         writel(val, MXC_CCM_CLPCR);
 440
 441         return 0;
 442 }
 443
 444 int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 445                         unsigned long rate_ckih1, unsigned long rate_ckih2)
 446 {
 447         int i;
 448         unsigned long r;
 449         struct device_node *np;
 450
 451         clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
 452         clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
 453         clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
 454         clk[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
 455
 456         clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
 457         clk[ldb_di1_div] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0);
 458         clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
 459                                 mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT);
 460         clk[di_pll4_podf] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
 461         clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
 462         clk[ldb_di0_div] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0);
 463         clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
 464                                 mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
 465         clk[ldb_di0_gate] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
 466         clk[ldb_di1_gate] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
 467         clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
 468                                 mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
 469         clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
 470                                 mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
 471         clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
 472                                 mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
 473         clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
 474         clk[tve_pred] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
 475         clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
 476         clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
 477         clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
 478         clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
 479         clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
 480         clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
 481         clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
 482                                 mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
 483         clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
 484         clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
 485         clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
 486         clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
 487         clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
 488
 489         clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
 490                                 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
 491         clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
 492         clk[cko1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
 493
 494         clk[cko2_sel] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
 495                                 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
 496         clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
 497         clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
 498
 499         for (i = 0; i < ARRAY_SIZE(clk); i++)
 500                 if (IS_ERR(clk[i]))
 501                         pr_err("i.MX53 clk %d: register failed with %ld\n",
 502                                 i, PTR_ERR(clk[i]));
 503
 504         np = of_find_compatible_node(NULL, NULL, "fsl,imx53-ccm");
 505         clk_data.clks = clk;
 506         clk_data.clk_num = ARRAY_SIZE(clk);
 507         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 508
 509         mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
 510
 511         clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
 512         clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
 513         clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
 514         clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
 515         clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
 516         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
 517         clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx53.0");
 518         clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx53.1");
 519         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.1");
 520         clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx53.1");
 521         clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx53.2");
 522         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.2");
 523         clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx53.2");
 524         clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
 525         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
 526         clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
 527
 528         /* set SDHC root clock to 200MHZ*/
 529         clk_set_rate(clk[esdhc_a_podf], 200000000);
 530         clk_set_rate(clk[esdhc_b_podf], 200000000);
 531
 532         /* System timer */
 533         mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT);
 534
 535         clk_prepare_enable(clk[iim_gate]);
 536         imx_print_silicon_rev("i.MX53", mx53_revision());
 537         clk_disable_unprepare(clk[iim_gate]);
 538
 539         r = clk_round_rate(clk[usboh3_per_gate], 54000000);
 540         clk_set_rate(clk[usboh3_per_gate], r);
 541
 542         return 0;
 543 }
 544
 545 #ifdef CONFIG_OF
 546 static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
 547                                    unsigned long *ckih1, unsigned long *ckih2)
 548 {
 549         struct device_node *np;
 550
 551         /* retrieve the freqency of fixed clocks from device tree */
 552         for_each_compatible_node(np, NULL, "fixed-clock") {
 553                 u32 rate;
 554                 if (of_property_read_u32(np, "clock-frequency", &rate))
 555                         continue;
 556
 557                 if (of_device_is_compatible(np, "fsl,imx-ckil"))
 558                         *ckil = rate;
 559                 else if (of_device_is_compatible(np, "fsl,imx-osc"))
 560                         *osc = rate;
 561                 else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
 562                         *ckih1 = rate;
 563                 else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
 564                         *ckih2 = rate;
 565         }
 566 }
 567
 568 int __init mx51_clocks_init_dt(void)
 569 {
 570         unsigned long ckil, osc, ckih1, ckih2;
 571
 572         clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
 573         return mx51_clocks_init(ckil, osc, ckih1, ckih2);
 574 }
 575
 576 int __init mx53_clocks_init_dt(void)
 577 {
 578         unsigned long ckil, osc, ckih1, ckih2;
 579
 580         clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
 581         return mx53_clocks_init(ckil, osc, ckih1, ckih2);
 582 }
 583 #endif