1 /* linux/arch/arm/mach-exynos4/gpiolib.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * EXYNOS4 - GPIOlib support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/irq.h>
16 #include <linux/gpio.h>
20 #include <plat/gpio-core.h>
21 #include <plat/gpio-cfg.h>
22 #include <plat/gpio-cfg-helpers.h>
24 static struct s3c_gpio_cfg gpio_cfg = {
25 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
26 .set_pull = s3c_gpio_setpull_updown,
27 .get_pull = s3c_gpio_getpull_updown,
30 static struct s3c_gpio_cfg gpio_cfg_noint = {
31 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
32 .set_pull = s3c_gpio_setpull_updown,
33 .get_pull = s3c_gpio_getpull_updown,
37 * Following are the gpio banks in v310.
39 * The 'config' member when left to NULL, is initialized to the default
40 * structure gpio_cfg in the init function below.
42 * The 'base' member is also initialized in the init function below.
43 * Note: The initialization of 'base' member of s3c_gpio_chip structure
44 * uses the above macro and depends on the banks being listed in order here.
46 static struct s3c_gpio_chip exynos4_gpio_part1_4bit[] = {
49 .base = EXYNOS4_GPA0(0),
50 .ngpio = EXYNOS4_GPIO_A0_NR,
55 .base = EXYNOS4_GPA1(0),
56 .ngpio = EXYNOS4_GPIO_A1_NR,
61 .base = EXYNOS4_GPB(0),
62 .ngpio = EXYNOS4_GPIO_B_NR,
67 .base = EXYNOS4_GPC0(0),
68 .ngpio = EXYNOS4_GPIO_C0_NR,
73 .base = EXYNOS4_GPC1(0),
74 .ngpio = EXYNOS4_GPIO_C1_NR,
79 .base = EXYNOS4_GPD0(0),
80 .ngpio = EXYNOS4_GPIO_D0_NR,
85 .base = EXYNOS4_GPD1(0),
86 .ngpio = EXYNOS4_GPIO_D1_NR,
91 .base = EXYNOS4_GPE0(0),
92 .ngpio = EXYNOS4_GPIO_E0_NR,
97 .base = EXYNOS4_GPE1(0),
98 .ngpio = EXYNOS4_GPIO_E1_NR,
103 .base = EXYNOS4_GPE2(0),
104 .ngpio = EXYNOS4_GPIO_E2_NR,
109 .base = EXYNOS4_GPE3(0),
110 .ngpio = EXYNOS4_GPIO_E3_NR,
115 .base = EXYNOS4_GPE4(0),
116 .ngpio = EXYNOS4_GPIO_E4_NR,
121 .base = EXYNOS4_GPF0(0),
122 .ngpio = EXYNOS4_GPIO_F0_NR,
127 .base = EXYNOS4_GPF1(0),
128 .ngpio = EXYNOS4_GPIO_F1_NR,
133 .base = EXYNOS4_GPF2(0),
134 .ngpio = EXYNOS4_GPIO_F2_NR,
139 .base = EXYNOS4_GPF3(0),
140 .ngpio = EXYNOS4_GPIO_F3_NR,
146 static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
149 .base = EXYNOS4_GPJ0(0),
150 .ngpio = EXYNOS4_GPIO_J0_NR,
155 .base = EXYNOS4_GPJ1(0),
156 .ngpio = EXYNOS4_GPIO_J1_NR,
161 .base = EXYNOS4_GPK0(0),
162 .ngpio = EXYNOS4_GPIO_K0_NR,
167 .base = EXYNOS4_GPK1(0),
168 .ngpio = EXYNOS4_GPIO_K1_NR,
173 .base = EXYNOS4_GPK2(0),
174 .ngpio = EXYNOS4_GPIO_K2_NR,
179 .base = EXYNOS4_GPK3(0),
180 .ngpio = EXYNOS4_GPIO_K3_NR,
185 .base = EXYNOS4_GPL0(0),
186 .ngpio = EXYNOS4_GPIO_L0_NR,
191 .base = EXYNOS4_GPL1(0),
192 .ngpio = EXYNOS4_GPIO_L1_NR,
197 .base = EXYNOS4_GPL2(0),
198 .ngpio = EXYNOS4_GPIO_L2_NR,
202 .base = (S5P_VA_GPIO2 + 0xC00),
203 .config = &gpio_cfg_noint,
204 .irq_base = IRQ_EINT(0),
206 .base = EXYNOS4_GPX0(0),
207 .ngpio = EXYNOS4_GPIO_X0_NR,
209 .to_irq = samsung_gpiolib_to_irq,
212 .base = (S5P_VA_GPIO2 + 0xC20),
213 .config = &gpio_cfg_noint,
214 .irq_base = IRQ_EINT(8),
216 .base = EXYNOS4_GPX1(0),
217 .ngpio = EXYNOS4_GPIO_X1_NR,
219 .to_irq = samsung_gpiolib_to_irq,
222 .base = (S5P_VA_GPIO2 + 0xC40),
223 .config = &gpio_cfg_noint,
224 .irq_base = IRQ_EINT(16),
226 .base = EXYNOS4_GPX2(0),
227 .ngpio = EXYNOS4_GPIO_X2_NR,
229 .to_irq = samsung_gpiolib_to_irq,
232 .base = (S5P_VA_GPIO2 + 0xC60),
233 .config = &gpio_cfg_noint,
234 .irq_base = IRQ_EINT(24),
236 .base = EXYNOS4_GPX3(0),
237 .ngpio = EXYNOS4_GPIO_X3_NR,
239 .to_irq = samsung_gpiolib_to_irq,
244 static struct s3c_gpio_chip exynos4_gpio_part3_4bit[] = {
247 .base = EXYNOS4_GPZ(0),
248 .ngpio = EXYNOS4_GPIO_Z_NR,
254 static __init int exynos4_gpiolib_init(void)
256 struct s3c_gpio_chip *chip;
262 chip = exynos4_gpio_part1_4bit;
263 nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit);
265 for (i = 0; i < nr_chips; i++, chip++) {
266 if (chip->config == NULL)
267 chip->config = &gpio_cfg;
268 if (chip->base == NULL)
269 chip->base = S5P_VA_GPIO1 + (i) * 0x20;
272 samsung_gpiolib_add_4bit_chips(exynos4_gpio_part1_4bit, nr_chips);
276 chip = exynos4_gpio_part2_4bit;
277 nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit);
279 for (i = 0; i < nr_chips; i++, chip++) {
280 if (chip->config == NULL)
281 chip->config = &gpio_cfg;
282 if (chip->base == NULL)
283 chip->base = S5P_VA_GPIO2 + (i) * 0x20;
286 samsung_gpiolib_add_4bit_chips(exynos4_gpio_part2_4bit, nr_chips);
290 chip = exynos4_gpio_part3_4bit;
291 nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit);
293 for (i = 0; i < nr_chips; i++, chip++) {
294 if (chip->config == NULL)
295 chip->config = &gpio_cfg;
296 if (chip->base == NULL)
297 chip->base = S5P_VA_GPIO3 + (i) * 0x20;
300 samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips);
304 core_initcall(exynos4_gpiolib_init);