arch/arm/mach-exynos4/cpu.c

   1 /* linux/arch/arm/mach-exynos4/cpu.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/sched.h>
  12 #include <linux/sysdev.h>
  13
  14 #include <asm/mach/map.h>
  15 #include <asm/mach/irq.h>
  16
  17 #include <asm/proc-fns.h>
  18 #include <asm/hardware/cache-l2x0.h>
  19
  20 #include <plat/cpu.h>
  21 #include <plat/clock.h>
  22 #include <plat/exynos4.h>
  23 #include <plat/sdhci.h>
  24
  25 #include <mach/regs-irq.h>
  26
  27 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
  28                          unsigned int irq_start);
  29 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
  30
  31 /* Initial IO mappings */
  32 static struct map_desc exynos4_iodesc[] __initdata = {
  33         {
  34                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
  35                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
  36                 .length         = SZ_4K,
  37                 .type           = MT_DEVICE,
  38         }, {
  39                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
  40                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
  41                 .length         = SZ_4K,
  42                 .type           = MT_DEVICE,
  43         }, {
  44                 .virtual        = (unsigned long)S5P_VA_CMU,
  45                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
  46                 .length         = SZ_128K,
  47                 .type           = MT_DEVICE,
  48         }, {
  49                 .virtual        = (unsigned long)S5P_VA_PMU,
  50                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
  51                 .length         = SZ_64K,
  52                 .type           = MT_DEVICE,
  53         }, {
  54                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
  55                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
  56                 .length         = SZ_4K,
  57                 .type           = MT_DEVICE,
  58         }, {
  59                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
  60                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
  61                 .length         = SZ_8K,
  62                 .type           = MT_DEVICE,
  63         }, {
  64                 .virtual        = (unsigned long)S5P_VA_L2CC,
  65                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
  66                 .length         = SZ_4K,
  67                 .type           = MT_DEVICE,
  68         }, {
  69                 .virtual        = (unsigned long)S5P_VA_GPIO1,
  70                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
  71                 .length         = SZ_4K,
  72                 .type           = MT_DEVICE,
  73         }, {
  74                 .virtual        = (unsigned long)S5P_VA_GPIO2,
  75                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
  76                 .length         = SZ_4K,
  77                 .type           = MT_DEVICE,
  78         }, {
  79                 .virtual        = (unsigned long)S5P_VA_GPIO3,
  80                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
  81                 .length         = SZ_256,
  82                 .type           = MT_DEVICE,
  83         }, {
  84                 .virtual        = (unsigned long)S5P_VA_DMC0,
  85                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
  86                 .length         = SZ_4K,
  87                 .type           = MT_DEVICE,
  88         }, {
  89                 .virtual        = (unsigned long)S3C_VA_UART,
  90                 .pfn            = __phys_to_pfn(S3C_PA_UART),
  91                 .length         = SZ_512K,
  92                 .type           = MT_DEVICE,
  93         }, {
  94                 .virtual        = (unsigned long)S5P_VA_SROMC,
  95                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
  96                 .length         = SZ_4K,
  97                 .type           = MT_DEVICE,
  98         },
  99 };
 100
 101 static void exynos4_idle(void)
 102 {
 103         if (!need_resched())
 104                 cpu_do_idle();
 105
 106         local_irq_enable();
 107 }
 108
 109 /*
 110  * exynos4_map_io
 111  *
 112  * register the standard cpu IO areas
 113  */
 114 void __init exynos4_map_io(void)
 115 {
 116         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 117
 118         /* initialize device information early */
 119         exynos4_default_sdhci0();
 120         exynos4_default_sdhci1();
 121         exynos4_default_sdhci2();
 122         exynos4_default_sdhci3();
 123 }
 124
 125 void __init exynos4_init_clocks(int xtal)
 126 {
 127         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 128
 129         s3c24xx_register_baseclocks(xtal);
 130         s5p_register_clocks(xtal);
 131         exynos4_register_clocks();
 132         exynos4_setup_clocks();
 133 }
 134
 135 void __init exynos4_init_irq(void)
 136 {
 137         int irq;
 138
 139         gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
 140
 141         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
 142
 143                 /*
 144                  * From SPI(0) to SPI(39) and SPI(51), SPI(53) are
 145                  * connected to the interrupt combiner. These irqs
 146                  * should be initialized to support cascade interrupt.
 147                  */
 148                 if ((irq >= 40) && !(irq == 51) && !(irq == 53))
 149                         continue;
 150
 151                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
 152                                 COMBINER_IRQ(irq, 0));
 153                 combiner_cascade_irq(irq, IRQ_SPI(irq));
 154         }
 155
 156         /* The parameters of s5p_init_irq() are for VIC init.
 157          * Theses parameters should be NULL and 0 because EXYNOS4
 158          * uses GIC instead of VIC.
 159          */
 160         s5p_init_irq(NULL, 0);
 161 }
 162
 163 struct sysdev_class exynos4_sysclass = {
 164         .name   = "exynos4-core",
 165 };
 166
 167 static struct sys_device exynos4_sysdev = {
 168         .cls    = &exynos4_sysclass,
 169 };
 170
 171 static int __init exynos4_core_init(void)
 172 {
 173         return sysdev_class_register(&exynos4_sysclass);
 174 }
 175
 176 core_initcall(exynos4_core_init);
 177
 178 #ifdef CONFIG_CACHE_L2X0
 179 static int __init exynos4_l2x0_cache_init(void)
 180 {
 181         /* TAG, Data Latency Control: 2cycle */
 182         __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 183         __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 184
 185         /* L2X0 Prefetch Control */
 186         __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 187
 188         /* L2X0 Power Control */
 189         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
 190                      S5P_VA_L2CC + L2X0_POWER_CTRL);
 191
 192         l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
 193
 194         return 0;
 195 }
 196
 197 early_initcall(exynos4_l2x0_cache_init);
 198 #endif
 199
 200 int __init exynos4_init(void)
 201 {
 202         printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
 203
 204         /* set idle function */
 205         pm_idle = exynos4_idle;
 206
 207         return sysdev_register(&exynos4_sysdev);
 208 }