1 /* linux/arch/arm/mach-exynos4/irq-eint.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * EXYNOS4 - IRQ EINT support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
17 #include <linux/sysdev.h>
18 #include <linux/gpio.h>
22 #include <plat/gpio-cfg.h>
24 #include <mach/regs-gpio.h>
26 #include <asm/mach/irq.h>
28 static DEFINE_SPINLOCK(eint_lock);
30 static unsigned int eint0_15_data[16];
32 static unsigned int exynos4_get_irq_nr(unsigned int number)
38 ret = (number + IRQ_EINT0);
41 ret = (number + (IRQ_EINT4 - 4));
44 ret = (number + (IRQ_EINT8 - 8));
47 printk(KERN_ERR "number available : %d\n", number);
53 static inline void exynos4_irq_eint_mask(struct irq_data *data)
57 spin_lock(&eint_lock);
58 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
59 mask |= eint_irq_to_bit(data->irq);
60 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
61 spin_unlock(&eint_lock);
64 static void exynos4_irq_eint_unmask(struct irq_data *data)
68 spin_lock(&eint_lock);
69 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
70 mask &= ~(eint_irq_to_bit(data->irq));
71 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
72 spin_unlock(&eint_lock);
75 static inline void exynos4_irq_eint_ack(struct irq_data *data)
77 __raw_writel(eint_irq_to_bit(data->irq),
78 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
81 static void exynos4_irq_eint_maskack(struct irq_data *data)
83 exynos4_irq_eint_mask(data);
84 exynos4_irq_eint_ack(data);
87 static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
89 int offs = EINT_OFFSET(data->irq);
95 case IRQ_TYPE_EDGE_RISING:
96 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
99 case IRQ_TYPE_EDGE_FALLING:
100 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
103 case IRQ_TYPE_EDGE_BOTH:
104 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
107 case IRQ_TYPE_LEVEL_LOW:
108 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
111 case IRQ_TYPE_LEVEL_HIGH:
112 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
116 printk(KERN_ERR "No such irq type %d", type);
120 shift = (offs & 0x7) * 4;
123 spin_lock(&eint_lock);
124 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
126 ctrl |= newvalue << shift;
127 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
128 spin_unlock(&eint_lock);
132 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
135 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
138 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
141 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
144 printk(KERN_ERR "No such irq number %d", offs);
150 static struct irq_chip exynos4_irq_eint = {
151 .name = "exynos4-eint",
152 .irq_mask = exynos4_irq_eint_mask,
153 .irq_unmask = exynos4_irq_eint_unmask,
154 .irq_mask_ack = exynos4_irq_eint_maskack,
155 .irq_ack = exynos4_irq_eint_ack,
156 .irq_set_type = exynos4_irq_eint_set_type,
158 .irq_set_wake = s3c_irqext_wake,
162 /* exynos4_irq_demux_eint
164 * This function demuxes the IRQ from from EINTs 16 to 31.
165 * It is designed to be inlined into the specific handler
166 * s5p_irq_demux_eintX_Y.
168 * Each EINT pend/mask registers handle eight of them.
170 static inline void exynos4_irq_demux_eint(unsigned int start)
174 u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
175 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
181 irq = fls(status) - 1;
182 generic_handle_irq(irq + start);
183 status &= ~(1 << irq);
187 static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
189 struct irq_chip *chip = irq_get_chip(irq);
190 chained_irq_enter(chip, desc);
191 exynos4_irq_demux_eint(IRQ_EINT(16));
192 exynos4_irq_demux_eint(IRQ_EINT(24));
193 chained_irq_exit(chip, desc);
196 static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
198 u32 *irq_data = irq_get_handler_data(irq);
199 struct irq_chip *chip = irq_get_chip(irq);
201 chained_irq_enter(chip, desc);
202 chip->irq_mask(&desc->irq_data);
205 chip->irq_ack(&desc->irq_data);
207 generic_handle_irq(*irq_data);
209 chip->irq_unmask(&desc->irq_data);
210 chained_irq_exit(chip, desc);
213 int __init exynos4_init_irq_eint(void)
217 for (irq = 0 ; irq <= 31 ; irq++) {
218 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
220 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
223 irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
225 for (irq = 0 ; irq <= 15 ; irq++) {
226 eint0_15_data[irq] = IRQ_EINT(irq);
228 irq_set_handler_data(exynos4_get_irq_nr(irq),
229 &eint0_15_data[irq]);
230 irq_set_chained_handler(exynos4_get_irq_nr(irq),
231 exynos4_irq_eint0_15);
237 arch_initcall(exynos4_init_irq_eint);