arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/irqchip.h>
  16 #include <linux/io.h>
  17 #include <linux/device.h>
  18 #include <linux/gpio.h>
  19 #include <linux/sched.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/of.h>
  22 #include <linux/of_fdt.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/export.h>
  25 #include <linux/irqdomain.h>
  26 #include <linux/irqchip.h>
  27 #include <linux/of_address.h>
  28 #include <linux/clocksource.h>
  29 #include <linux/clk-provider.h>
  30 #include <linux/irqchip/arm-gic.h>
  31
  32 #include <asm/proc-fns.h>
  33 #include <asm/exception.h>
  34 #include <asm/hardware/cache-l2x0.h>
  35 #include <asm/mach/map.h>
  36 #include <asm/mach/irq.h>
  37 #include <asm/cacheflush.h>
  38
  39 #include <mach/regs-irq.h>
  40 #include <mach/regs-pmu.h>
  41 #include <mach/regs-gpio.h>
  42
  43 #include <plat/cpu.h>
  44 #include <plat/devs.h>
  45 #include <plat/pm.h>
  46 #include <plat/sdhci.h>
  47 #include <plat/gpio-cfg.h>
  48 #include <plat/adc-core.h>
  49 #include <plat/fb-core.h>
  50 #include <plat/fimc-core.h>
  51 #include <plat/iic-core.h>
  52 #include <plat/tv-core.h>
  53 #include <plat/spi-core.h>
  54 #include <plat/regs-serial.h>
  55
  56 #include "common.h"
  57 #define L2_AUX_VAL 0x7C470001
  58 #define L2_AUX_MASK 0xC200ffff
  59
  60 static const char name_exynos4210[] = "EXYNOS4210";
  61 static const char name_exynos4212[] = "EXYNOS4212";
  62 static const char name_exynos4412[] = "EXYNOS4412";
  63 static const char name_exynos5250[] = "EXYNOS5250";
  64 static const char name_exynos5440[] = "EXYNOS5440";
  65
  66 static void exynos4_map_io(void);
  67 static void exynos5_map_io(void);
  68 static void exynos5440_map_io(void);
  69 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
  70 static int exynos_init(void);
  71
  72 unsigned long xxti_f = 0, xusbxti_f = 0;
  73
  74 static struct cpu_table cpu_ids[] __initdata = {
  75         {
  76                 .idcode         = EXYNOS4210_CPU_ID,
  77                 .idmask         = EXYNOS4_CPU_MASK,
  78                 .map_io         = exynos4_map_io,
  79                 .init_uarts     = exynos4_init_uarts,
  80                 .init           = exynos_init,
  81                 .name           = name_exynos4210,
  82         }, {
  83                 .idcode         = EXYNOS4212_CPU_ID,
  84                 .idmask         = EXYNOS4_CPU_MASK,
  85                 .map_io         = exynos4_map_io,
  86                 .init_uarts     = exynos4_init_uarts,
  87                 .init           = exynos_init,
  88                 .name           = name_exynos4212,
  89         }, {
  90                 .idcode         = EXYNOS4412_CPU_ID,
  91                 .idmask         = EXYNOS4_CPU_MASK,
  92                 .map_io         = exynos4_map_io,
  93                 .init_uarts     = exynos4_init_uarts,
  94                 .init           = exynos_init,
  95                 .name           = name_exynos4412,
  96         }, {
  97                 .idcode         = EXYNOS5250_SOC_ID,
  98                 .idmask         = EXYNOS5_SOC_MASK,
  99                 .map_io         = exynos5_map_io,
 100                 .init           = exynos_init,
 101                 .name           = name_exynos5250,
 102         }, {
 103                 .idcode         = EXYNOS5440_SOC_ID,
 104                 .idmask         = EXYNOS5_SOC_MASK,
 105                 .map_io         = exynos5440_map_io,
 106                 .init           = exynos_init,
 107                 .name           = name_exynos5440,
 108         },
 109 };
 110
 111 /* Initial IO mappings */
 112
 113 static struct map_desc exynos_iodesc[] __initdata = {
 114         {
 115                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 116                 .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
 117                 .length         = SZ_4K,
 118                 .type           = MT_DEVICE,
 119         },
 120 };
 121
 122 static struct map_desc exynos4_iodesc[] __initdata = {
 123         {
 124                 .virtual        = (unsigned long)S3C_VA_SYS,
 125                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 126                 .length         = SZ_64K,
 127                 .type           = MT_DEVICE,
 128         }, {
 129                 .virtual        = (unsigned long)S3C_VA_TIMER,
 130                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 131                 .length         = SZ_16K,
 132                 .type           = MT_DEVICE,
 133         }, {
 134                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 135                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 136                 .length         = SZ_4K,
 137                 .type           = MT_DEVICE,
 138         }, {
 139                 .virtual        = (unsigned long)S5P_VA_SROMC,
 140                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 141                 .length         = SZ_4K,
 142                 .type           = MT_DEVICE,
 143         }, {
 144                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 145                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 146                 .length         = SZ_4K,
 147                 .type           = MT_DEVICE,
 148         }, {
 149                 .virtual        = (unsigned long)S5P_VA_PMU,
 150                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 151                 .length         = SZ_64K,
 152                 .type           = MT_DEVICE,
 153         }, {
 154                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 155                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 156                 .length         = SZ_4K,
 157                 .type           = MT_DEVICE,
 158         }, {
 159                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 160                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 161                 .length         = SZ_64K,
 162                 .type           = MT_DEVICE,
 163         }, {
 164                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 165                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 166                 .length         = SZ_64K,
 167                 .type           = MT_DEVICE,
 168         }, {
 169                 .virtual        = (unsigned long)S3C_VA_UART,
 170                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 171                 .length         = SZ_512K,
 172                 .type           = MT_DEVICE,
 173         }, {
 174                 .virtual        = (unsigned long)S5P_VA_CMU,
 175                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 176                 .length         = SZ_128K,
 177                 .type           = MT_DEVICE,
 178         }, {
 179                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 180                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 181                 .length         = SZ_8K,
 182                 .type           = MT_DEVICE,
 183         }, {
 184                 .virtual        = (unsigned long)S5P_VA_L2CC,
 185                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 186                 .length         = SZ_4K,
 187                 .type           = MT_DEVICE,
 188         }, {
 189                 .virtual        = (unsigned long)S5P_VA_DMC0,
 190                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 191                 .length         = SZ_64K,
 192                 .type           = MT_DEVICE,
 193         }, {
 194                 .virtual        = (unsigned long)S5P_VA_DMC1,
 195                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 196                 .length         = SZ_64K,
 197                 .type           = MT_DEVICE,
 198         }, {
 199                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 200                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 201                 .length         = SZ_4K,
 202                 .type           = MT_DEVICE,
 203         },
 204 };
 205
 206 static struct map_desc exynos4_iodesc0[] __initdata = {
 207         {
 208                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 209                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 210                 .length         = SZ_4K,
 211                 .type           = MT_DEVICE,
 212         },
 213 };
 214
 215 static struct map_desc exynos4_iodesc1[] __initdata = {
 216         {
 217                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 218                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 219                 .length         = SZ_4K,
 220                 .type           = MT_DEVICE,
 221         },
 222 };
 223
 224 static struct map_desc exynos5_iodesc[] __initdata = {
 225         {
 226                 .virtual        = (unsigned long)S3C_VA_SYS,
 227                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 228                 .length         = SZ_64K,
 229                 .type           = MT_DEVICE,
 230         }, {
 231                 .virtual        = (unsigned long)S3C_VA_TIMER,
 232                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 233                 .length         = SZ_16K,
 234                 .type           = MT_DEVICE,
 235         }, {
 236                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 237                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 238                 .length         = SZ_4K,
 239                 .type           = MT_DEVICE,
 240         }, {
 241                 .virtual        = (unsigned long)S5P_VA_SROMC,
 242                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 243                 .length         = SZ_4K,
 244                 .type           = MT_DEVICE,
 245         }, {
 246                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 247                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 248                 .length         = SZ_4K,
 249                 .type           = MT_DEVICE,
 250         }, {
 251                 .virtual        = (unsigned long)S5P_VA_CMU,
 252                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 253                 .length         = 144 * SZ_1K,
 254                 .type           = MT_DEVICE,
 255         }, {
 256                 .virtual        = (unsigned long)S5P_VA_PMU,
 257                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 258                 .length         = SZ_64K,
 259                 .type           = MT_DEVICE,
 260         }, {
 261                 .virtual        = (unsigned long)S3C_VA_UART,
 262                 .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
 263                 .length         = SZ_512K,
 264                 .type           = MT_DEVICE,
 265         },
 266 };
 267
 268 static struct map_desc exynos5440_iodesc0[] __initdata = {
 269         {
 270                 .virtual        = (unsigned long)S3C_VA_UART,
 271                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_UART0),
 272                 .length         = SZ_512K,
 273                 .type           = MT_DEVICE,
 274         },
 275 };
 276
 277 void exynos4_restart(char mode, const char *cmd)
 278 {
 279         __raw_writel(0x1, S5P_SWRESET);
 280 }
 281
 282 void exynos5_restart(char mode, const char *cmd)
 283 {
 284         struct device_node *np;
 285         u32 val;
 286         void __iomem *addr;
 287
 288         if (of_machine_is_compatible("samsung,exynos5250")) {
 289                 val = 0x1;
 290                 addr = EXYNOS_SWRESET;
 291         } else if (of_machine_is_compatible("samsung,exynos5440")) {
 292                 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
 293                 addr = of_iomap(np, 0) + 0xcc;
 294                 val = (0xfff << 20) | (0x1 << 16);
 295         } else {
 296                 pr_err("%s: cannot support non-DT\n", __func__);
 297                 return;
 298         }
 299
 300         __raw_writel(val, addr);
 301 }
 302
 303 void __init exynos_init_late(void)
 304 {
 305         if (of_machine_is_compatible("samsung,exynos5440"))
 306                 /* to be supported later */
 307                 return;
 308
 309         exynos_pm_late_initcall();
 310 }
 311
 312 #ifdef CONFIG_OF
 313 int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
 314                                         int depth, void *data)
 315 {
 316         struct map_desc iodesc;
 317         __be32 *reg;
 318         unsigned long len;
 319
 320         if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
 321                 !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
 322                 return 0;
 323
 324         reg = of_get_flat_dt_prop(node, "reg", &len);
 325         if (reg == NULL || len != (sizeof(unsigned long) * 2))
 326                 return 0;
 327
 328         iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
 329         iodesc.length = be32_to_cpu(reg[1]) - 1;
 330         iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
 331         iodesc.type = MT_DEVICE;
 332         iotable_init(&iodesc, 1);
 333         return 1;
 334 }
 335 #endif
 336
 337 /*
 338  * exynos_map_io
 339  *
 340  * register the standard cpu IO areas
 341  */
 342
 343 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 344 {
 345 #ifdef CONFIG_OF
 346         if (initial_boot_params)
 347                 of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
 348         else
 349 #endif
 350                 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
 351
 352         if (mach_desc)
 353                 iotable_init(mach_desc, size);
 354
 355         /* detect cpu id and rev. */
 356         s5p_init_cpu(S5P_VA_CHIPID);
 357
 358         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 359 }
 360
 361 static void __init exynos4_map_io(void)
 362 {
 363         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 364
 365         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 366                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 367         else
 368                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 369
 370         /* initialize device information early */
 371         exynos4_default_sdhci0();
 372         exynos4_default_sdhci1();
 373         exynos4_default_sdhci2();
 374         exynos4_default_sdhci3();
 375
 376         s3c_adc_setname("samsung-adc-v3");
 377
 378         s3c_fimc_setname(0, "exynos4-fimc");
 379         s3c_fimc_setname(1, "exynos4-fimc");
 380         s3c_fimc_setname(2, "exynos4-fimc");
 381         s3c_fimc_setname(3, "exynos4-fimc");
 382
 383         s3c_sdhci_setname(0, "exynos4-sdhci");
 384         s3c_sdhci_setname(1, "exynos4-sdhci");
 385         s3c_sdhci_setname(2, "exynos4-sdhci");
 386         s3c_sdhci_setname(3, "exynos4-sdhci");
 387
 388         /* The I2C bus controllers are directly compatible with s3c2440 */
 389         s3c_i2c0_setname("s3c2440-i2c");
 390         s3c_i2c1_setname("s3c2440-i2c");
 391         s3c_i2c2_setname("s3c2440-i2c");
 392
 393         s5p_fb_setname(0, "exynos4-fb");
 394         s5p_hdmi_setname("exynos4-hdmi");
 395
 396         s3c64xx_spi_setname("exynos4210-spi");
 397 }
 398
 399 static void __init exynos5_map_io(void)
 400 {
 401         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 402 }
 403
 404 static void __init exynos5440_map_io(void)
 405 {
 406         iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 407 }
 408
 409 void __init exynos_init_time(void)
 410 {
 411         if (of_have_populated_dt()) {
 412 #ifdef CONFIG_OF
 413                 of_clk_init(NULL);
 414                 clocksource_of_init();
 415 #endif
 416         } else {
 417                 /* todo: remove after migrating legacy E4 platforms to dt */
 418 #ifdef CONFIG_ARCH_EXYNOS4
 419                 exynos4_clk_init(NULL);
 420                 exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
 421 #endif
 422                 mct_init();
 423         }
 424 }
 425
 426 void __init exynos4_init_irq(void)
 427 {
 428         unsigned int gic_bank_offset;
 429
 430         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 431
 432         if (!of_have_populated_dt())
 433                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 434 #ifdef CONFIG_OF
 435         else
 436                 irqchip_init();
 437 #endif
 438
 439         if (!of_have_populated_dt())
 440                 combiner_init(S5P_VA_COMBINER_BASE, NULL);
 441
 442         /*
 443          * The parameters of s5p_init_irq() are for VIC init.
 444          * Theses parameters should be NULL and 0 because EXYNOS4
 445          * uses GIC instead of VIC.
 446          */
 447         s5p_init_irq(NULL, 0);
 448 }
 449
 450 void __init exynos5_init_irq(void)
 451 {
 452 #ifdef CONFIG_OF
 453         irqchip_init();
 454 #endif
 455         /*
 456          * The parameters of s5p_init_irq() are for VIC init.
 457          * Theses parameters should be NULL and 0 because EXYNOS4
 458          * uses GIC instead of VIC.
 459          */
 460         if (!of_machine_is_compatible("samsung,exynos5440"))
 461                 s5p_init_irq(NULL, 0);
 462
 463         gic_arch_extn.irq_set_wake = s3c_irq_wake;
 464 }
 465
 466 struct bus_type exynos_subsys = {
 467         .name           = "exynos-core",
 468         .dev_name       = "exynos-core",
 469 };
 470
 471 static struct device exynos4_dev = {
 472         .bus    = &exynos_subsys,
 473 };
 474
 475 static int __init exynos_core_init(void)
 476 {
 477         return subsys_system_register(&exynos_subsys, NULL);
 478 }
 479 core_initcall(exynos_core_init);
 480
 481 #ifdef CONFIG_CACHE_L2X0
 482 static int __init exynos4_l2x0_cache_init(void)
 483 {
 484         int ret;
 485
 486         if (soc_is_exynos5250() || soc_is_exynos5440())
 487                 return 0;
 488
 489         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 490         if (!ret) {
 491                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 492                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 493                 return 0;
 494         }
 495
 496         if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
 497                 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
 498                 /* TAG, Data Latency Control: 2 cycles */
 499                 l2x0_saved_regs.tag_latency = 0x110;
 500
 501                 if (soc_is_exynos4212() || soc_is_exynos4412())
 502                         l2x0_saved_regs.data_latency = 0x120;
 503                 else
 504                         l2x0_saved_regs.data_latency = 0x110;
 505
 506                 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
 507                 l2x0_saved_regs.pwr_ctrl =
 508                         (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
 509
 510                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 511
 512                 __raw_writel(l2x0_saved_regs.tag_latency,
 513                                 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 514                 __raw_writel(l2x0_saved_regs.data_latency,
 515                                 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 516
 517                 /* L2X0 Prefetch Control */
 518                 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
 519                                 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 520
 521                 /* L2X0 Power Control */
 522                 __raw_writel(l2x0_saved_regs.pwr_ctrl,
 523                                 S5P_VA_L2CC + L2X0_POWER_CTRL);
 524
 525                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 526                 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
 527         }
 528
 529         l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
 530         return 0;
 531 }
 532 early_initcall(exynos4_l2x0_cache_init);
 533 #endif
 534
 535 static int __init exynos_init(void)
 536 {
 537         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 538
 539         return device_register(&exynos4_dev);
 540 }
 541
 542 /* uart registration process */
 543
 544 static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 545 {
 546         struct s3c2410_uartcfg *tcfg = cfg;
 547         u32 ucnt;
 548
 549         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 550                 tcfg->has_fracval = 1;
 551
 552         s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 553 }
 554
 555 static void __iomem *exynos_eint_base;
 556
 557 static DEFINE_SPINLOCK(eint_lock);
 558
 559 static unsigned int eint0_15_data[16];
 560
 561 static inline int exynos4_irq_to_gpio(unsigned int irq)
 562 {
 563         if (irq < IRQ_EINT(0))
 564                 return -EINVAL;
 565
 566         irq -= IRQ_EINT(0);
 567         if (irq < 8)
 568                 return EXYNOS4_GPX0(irq);
 569
 570         irq -= 8;
 571         if (irq < 8)
 572                 return EXYNOS4_GPX1(irq);
 573
 574         irq -= 8;
 575         if (irq < 8)
 576                 return EXYNOS4_GPX2(irq);
 577
 578         irq -= 8;
 579         if (irq < 8)
 580                 return EXYNOS4_GPX3(irq);
 581
 582         return -EINVAL;
 583 }
 584
 585 static inline int exynos5_irq_to_gpio(unsigned int irq)
 586 {
 587         if (irq < IRQ_EINT(0))
 588                 return -EINVAL;
 589
 590         irq -= IRQ_EINT(0);
 591         if (irq < 8)
 592                 return EXYNOS5_GPX0(irq);
 593
 594         irq -= 8;
 595         if (irq < 8)
 596                 return EXYNOS5_GPX1(irq);
 597
 598         irq -= 8;
 599         if (irq < 8)
 600                 return EXYNOS5_GPX2(irq);
 601
 602         irq -= 8;
 603         if (irq < 8)
 604                 return EXYNOS5_GPX3(irq);
 605
 606         return -EINVAL;
 607 }
 608
 609 static unsigned int exynos4_eint0_15_src_int[16] = {
 610         EXYNOS4_IRQ_EINT0,
 611         EXYNOS4_IRQ_EINT1,
 612         EXYNOS4_IRQ_EINT2,
 613         EXYNOS4_IRQ_EINT3,
 614         EXYNOS4_IRQ_EINT4,
 615         EXYNOS4_IRQ_EINT5,
 616         EXYNOS4_IRQ_EINT6,
 617         EXYNOS4_IRQ_EINT7,
 618         EXYNOS4_IRQ_EINT8,
 619         EXYNOS4_IRQ_EINT9,
 620         EXYNOS4_IRQ_EINT10,
 621         EXYNOS4_IRQ_EINT11,
 622         EXYNOS4_IRQ_EINT12,
 623         EXYNOS4_IRQ_EINT13,
 624         EXYNOS4_IRQ_EINT14,
 625         EXYNOS4_IRQ_EINT15,
 626 };
 627
 628 static unsigned int exynos5_eint0_15_src_int[16] = {
 629         EXYNOS5_IRQ_EINT0,
 630         EXYNOS5_IRQ_EINT1,
 631         EXYNOS5_IRQ_EINT2,
 632         EXYNOS5_IRQ_EINT3,
 633         EXYNOS5_IRQ_EINT4,
 634         EXYNOS5_IRQ_EINT5,
 635         EXYNOS5_IRQ_EINT6,
 636         EXYNOS5_IRQ_EINT7,
 637         EXYNOS5_IRQ_EINT8,
 638         EXYNOS5_IRQ_EINT9,
 639         EXYNOS5_IRQ_EINT10,
 640         EXYNOS5_IRQ_EINT11,
 641         EXYNOS5_IRQ_EINT12,
 642         EXYNOS5_IRQ_EINT13,
 643         EXYNOS5_IRQ_EINT14,
 644         EXYNOS5_IRQ_EINT15,
 645 };
 646 static inline void exynos_irq_eint_mask(struct irq_data *data)
 647 {
 648         u32 mask;
 649
 650         spin_lock(&eint_lock);
 651         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 652         mask |= EINT_OFFSET_BIT(data->irq);
 653         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 654         spin_unlock(&eint_lock);
 655 }
 656
 657 static void exynos_irq_eint_unmask(struct irq_data *data)
 658 {
 659         u32 mask;
 660
 661         spin_lock(&eint_lock);
 662         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 663         mask &= ~(EINT_OFFSET_BIT(data->irq));
 664         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 665         spin_unlock(&eint_lock);
 666 }
 667
 668 static inline void exynos_irq_eint_ack(struct irq_data *data)
 669 {
 670         __raw_writel(EINT_OFFSET_BIT(data->irq),
 671                      EINT_PEND(exynos_eint_base, data->irq));
 672 }
 673
 674 static void exynos_irq_eint_maskack(struct irq_data *data)
 675 {
 676         exynos_irq_eint_mask(data);
 677         exynos_irq_eint_ack(data);
 678 }
 679
 680 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 681 {
 682         int offs = EINT_OFFSET(data->irq);
 683         int shift;
 684         u32 ctrl, mask;
 685         u32 newvalue = 0;
 686
 687         switch (type) {
 688         case IRQ_TYPE_EDGE_RISING:
 689                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
 690                 break;
 691
 692         case IRQ_TYPE_EDGE_FALLING:
 693                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 694                 break;
 695
 696         case IRQ_TYPE_EDGE_BOTH:
 697                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 698                 break;
 699
 700         case IRQ_TYPE_LEVEL_LOW:
 701                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 702                 break;
 703
 704         case IRQ_TYPE_LEVEL_HIGH:
 705                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 706                 break;
 707
 708         default:
 709                 printk(KERN_ERR "No such irq type %d", type);
 710                 return -EINVAL;
 711         }
 712
 713         shift = (offs & 0x7) * 4;
 714         mask = 0x7 << shift;
 715
 716         spin_lock(&eint_lock);
 717         ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
 718         ctrl &= ~mask;
 719         ctrl |= newvalue << shift;
 720         __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
 721         spin_unlock(&eint_lock);
 722
 723         if (soc_is_exynos5250())
 724                 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 725         else
 726                 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 727
 728         return 0;
 729 }
 730
 731 static struct irq_chip exynos_irq_eint = {
 732         .name           = "exynos-eint",
 733         .irq_mask       = exynos_irq_eint_mask,
 734         .irq_unmask     = exynos_irq_eint_unmask,
 735         .irq_mask_ack   = exynos_irq_eint_maskack,
 736         .irq_ack        = exynos_irq_eint_ack,
 737         .irq_set_type   = exynos_irq_eint_set_type,
 738 #ifdef CONFIG_PM
 739         .irq_set_wake   = s3c_irqext_wake,
 740 #endif
 741 };
 742
 743 /*
 744  * exynos4_irq_demux_eint
 745  *
 746  * This function demuxes the IRQ from from EINTs 16 to 31.
 747  * It is designed to be inlined into the specific handler
 748  * s5p_irq_demux_eintX_Y.
 749  *
 750  * Each EINT pend/mask registers handle eight of them.
 751  */
 752 static inline void exynos_irq_demux_eint(unsigned int start)
 753 {
 754         unsigned int irq;
 755
 756         u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
 757         u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
 758
 759         status &= ~mask;
 760         status &= 0xff;
 761
 762         while (status) {
 763                 irq = fls(status) - 1;
 764                 generic_handle_irq(irq + start);
 765                 status &= ~(1 << irq);
 766         }
 767 }
 768
 769 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 770 {
 771         struct irq_chip *chip = irq_get_chip(irq);
 772         chained_irq_enter(chip, desc);
 773         exynos_irq_demux_eint(IRQ_EINT(16));
 774         exynos_irq_demux_eint(IRQ_EINT(24));
 775         chained_irq_exit(chip, desc);
 776 }
 777
 778 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 779 {
 780         u32 *irq_data = irq_get_handler_data(irq);
 781         struct irq_chip *chip = irq_get_chip(irq);
 782
 783         chained_irq_enter(chip, desc);
 784         generic_handle_irq(*irq_data);
 785         chained_irq_exit(chip, desc);
 786 }
 787
 788 static int __init exynos_init_irq_eint(void)
 789 {
 790         int irq;
 791
 792 #ifdef CONFIG_PINCTRL_SAMSUNG
 793         /*
 794          * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
 795          * functionality along with support for external gpio and wakeup
 796          * interrupts. If the samsung pinctrl driver is enabled and includes
 797          * the wakeup interrupt support, then the setting up external wakeup
 798          * interrupts here can be skipped. This check here is temporary to
 799          * allow exynos4 platforms that do not use Samsung pinctrl driver to
 800          * co-exist with platforms that do. When all of the Samsung Exynos4
 801          * platforms switch over to using the pinctrl driver, the wakeup
 802          * interrupt support code here can be completely removed.
 803          */
 804         static const struct of_device_id exynos_pinctrl_ids[] = {
 805                 { .compatible = "samsung,exynos4210-pinctrl", },
 806                 { .compatible = "samsung,exynos4x12-pinctrl", },
 807                 { .compatible = "samsung,exynos5250-pinctrl", },
 808         };
 809         struct device_node *pctrl_np, *wkup_np;
 810         const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
 811
 812         for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
 813                 if (of_device_is_available(pctrl_np)) {
 814                         wkup_np = of_find_compatible_node(pctrl_np, NULL,
 815                                                         wkup_compat);
 816                         if (wkup_np)
 817                                 return -ENODEV;
 818                 }
 819         }
 820 #endif
 821         if (soc_is_exynos5440())
 822                 return 0;
 823
 824         if (soc_is_exynos5250())
 825                 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
 826         else
 827                 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
 828
 829         if (exynos_eint_base == NULL) {
 830                 pr_err("unable to ioremap for EINT base address\n");
 831                 return -ENOMEM;
 832         }
 833
 834         for (irq = 0 ; irq <= 31 ; irq++) {
 835                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
 836                                          handle_level_irq);
 837                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
 838         }
 839
 840         irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 841
 842         for (irq = 0 ; irq <= 15 ; irq++) {
 843                 eint0_15_data[irq] = IRQ_EINT(irq);
 844
 845                 if (soc_is_exynos5250()) {
 846                         irq_set_handler_data(exynos5_eint0_15_src_int[irq],
 847                                              &eint0_15_data[irq]);
 848                         irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
 849                                                 exynos_irq_eint0_15);
 850                 } else {
 851                         irq_set_handler_data(exynos4_eint0_15_src_int[irq],
 852                                              &eint0_15_data[irq]);
 853                         irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
 854                                                 exynos_irq_eint0_15);
 855                 }
 856         }
 857
 858         return 0;
 859 }
 860 arch_initcall(exynos_init_irq_eint);