arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/io.h>
  16 #include <linux/device.h>
  17 #include <linux/gpio.h>
  18 #include <linux/sched.h>
  19 #include <linux/serial_core.h>
  20 #include <linux/of.h>
  21 #include <linux/of_fdt.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/export.h>
  24 #include <linux/irqdomain.h>
  25 #include <linux/of_address.h>
  26
  27 #include <asm/proc-fns.h>
  28 #include <asm/exception.h>
  29 #include <asm/hardware/cache-l2x0.h>
  30 #include <asm/hardware/gic.h>
  31 #include <asm/mach/map.h>
  32 #include <asm/mach/irq.h>
  33 #include <asm/cacheflush.h>
  34
  35 #include <mach/regs-irq.h>
  36 #include <mach/regs-pmu.h>
  37 #include <mach/regs-gpio.h>
  38 #include <mach/pmu.h>
  39
  40 #include <plat/cpu.h>
  41 #include <plat/clock.h>
  42 #include <plat/devs.h>
  43 #include <plat/pm.h>
  44 #include <plat/sdhci.h>
  45 #include <plat/gpio-cfg.h>
  46 #include <plat/adc-core.h>
  47 #include <plat/fb-core.h>
  48 #include <plat/fimc-core.h>
  49 #include <plat/iic-core.h>
  50 #include <plat/tv-core.h>
  51 #include <plat/spi-core.h>
  52 #include <plat/regs-serial.h>
  53
  54 #include "common.h"
  55 #define L2_AUX_VAL 0x7C470001
  56 #define L2_AUX_MASK 0xC200ffff
  57
  58 static const char name_exynos4210[] = "EXYNOS4210";
  59 static const char name_exynos4212[] = "EXYNOS4212";
  60 static const char name_exynos4412[] = "EXYNOS4412";
  61 static const char name_exynos5250[] = "EXYNOS5250";
  62 static const char name_exynos5440[] = "EXYNOS5440";
  63
  64 static void exynos4_map_io(void);
  65 static void exynos5_map_io(void);
  66 static void exynos5440_map_io(void);
  67 static void exynos4_init_clocks(int xtal);
  68 static void exynos5_init_clocks(int xtal);
  69 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
  70 static int exynos_init(void);
  71
  72 static struct cpu_table cpu_ids[] __initdata = {
  73         {
  74                 .idcode         = EXYNOS4210_CPU_ID,
  75                 .idmask         = EXYNOS4_CPU_MASK,
  76                 .map_io         = exynos4_map_io,
  77                 .init_clocks    = exynos4_init_clocks,
  78                 .init_uarts     = exynos4_init_uarts,
  79                 .init           = exynos_init,
  80                 .name           = name_exynos4210,
  81         }, {
  82                 .idcode         = EXYNOS4212_CPU_ID,
  83                 .idmask         = EXYNOS4_CPU_MASK,
  84                 .map_io         = exynos4_map_io,
  85                 .init_clocks    = exynos4_init_clocks,
  86                 .init_uarts     = exynos4_init_uarts,
  87                 .init           = exynos_init,
  88                 .name           = name_exynos4212,
  89         }, {
  90                 .idcode         = EXYNOS4412_CPU_ID,
  91                 .idmask         = EXYNOS4_CPU_MASK,
  92                 .map_io         = exynos4_map_io,
  93                 .init_clocks    = exynos4_init_clocks,
  94                 .init_uarts     = exynos4_init_uarts,
  95                 .init           = exynos_init,
  96                 .name           = name_exynos4412,
  97         }, {
  98                 .idcode         = EXYNOS5250_SOC_ID,
  99                 .idmask         = EXYNOS5_SOC_MASK,
 100                 .map_io         = exynos5_map_io,
 101                 .init_clocks    = exynos5_init_clocks,
 102                 .init           = exynos_init,
 103                 .name           = name_exynos5250,
 104         }, {
 105                 .idcode         = EXYNOS5440_SOC_ID,
 106                 .idmask         = EXYNOS5_SOC_MASK,
 107                 .map_io         = exynos5440_map_io,
 108                 .init           = exynos_init,
 109                 .name           = name_exynos5440,
 110         },
 111 };
 112
 113 /* Initial IO mappings */
 114
 115 static struct map_desc exynos_iodesc[] __initdata = {
 116         {
 117                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 118                 .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
 119                 .length         = SZ_4K,
 120                 .type           = MT_DEVICE,
 121         },
 122 };
 123
 124 #ifdef CONFIG_ARCH_EXYNOS5
 125 static struct map_desc exynos5440_iodesc[] __initdata = {
 126         {
 127                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 128                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
 129                 .length         = SZ_4K,
 130                 .type           = MT_DEVICE,
 131         },
 132 };
 133 #endif
 134
 135 static struct map_desc exynos4_iodesc[] __initdata = {
 136         {
 137                 .virtual        = (unsigned long)S3C_VA_SYS,
 138                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 139                 .length         = SZ_64K,
 140                 .type           = MT_DEVICE,
 141         }, {
 142                 .virtual        = (unsigned long)S3C_VA_TIMER,
 143                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 144                 .length         = SZ_16K,
 145                 .type           = MT_DEVICE,
 146         }, {
 147                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 148                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 149                 .length         = SZ_4K,
 150                 .type           = MT_DEVICE,
 151         }, {
 152                 .virtual        = (unsigned long)S5P_VA_SROMC,
 153                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 154                 .length         = SZ_4K,
 155                 .type           = MT_DEVICE,
 156         }, {
 157                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 158                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 159                 .length         = SZ_4K,
 160                 .type           = MT_DEVICE,
 161         }, {
 162                 .virtual        = (unsigned long)S5P_VA_PMU,
 163                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 164                 .length         = SZ_64K,
 165                 .type           = MT_DEVICE,
 166         }, {
 167                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 168                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 169                 .length         = SZ_4K,
 170                 .type           = MT_DEVICE,
 171         }, {
 172                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 173                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 174                 .length         = SZ_64K,
 175                 .type           = MT_DEVICE,
 176         }, {
 177                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 178                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 179                 .length         = SZ_64K,
 180                 .type           = MT_DEVICE,
 181         }, {
 182                 .virtual        = (unsigned long)S3C_VA_UART,
 183                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 184                 .length         = SZ_512K,
 185                 .type           = MT_DEVICE,
 186         }, {
 187                 .virtual        = (unsigned long)S5P_VA_CMU,
 188                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 189                 .length         = SZ_128K,
 190                 .type           = MT_DEVICE,
 191         }, {
 192                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 193                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 194                 .length         = SZ_8K,
 195                 .type           = MT_DEVICE,
 196         }, {
 197                 .virtual        = (unsigned long)S5P_VA_L2CC,
 198                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 199                 .length         = SZ_4K,
 200                 .type           = MT_DEVICE,
 201         }, {
 202                 .virtual        = (unsigned long)S5P_VA_DMC0,
 203                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 204                 .length         = SZ_64K,
 205                 .type           = MT_DEVICE,
 206         }, {
 207                 .virtual        = (unsigned long)S5P_VA_DMC1,
 208                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 209                 .length         = SZ_64K,
 210                 .type           = MT_DEVICE,
 211         }, {
 212                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 213                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 214                 .length         = SZ_4K,
 215                 .type           = MT_DEVICE,
 216         },
 217 };
 218
 219 static struct map_desc exynos4_iodesc0[] __initdata = {
 220         {
 221                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 222                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 223                 .length         = SZ_4K,
 224                 .type           = MT_DEVICE,
 225         },
 226 };
 227
 228 static struct map_desc exynos4_iodesc1[] __initdata = {
 229         {
 230                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 231                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 232                 .length         = SZ_4K,
 233                 .type           = MT_DEVICE,
 234         },
 235 };
 236
 237 static struct map_desc exynos5_iodesc[] __initdata = {
 238         {
 239                 .virtual        = (unsigned long)S3C_VA_SYS,
 240                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 241                 .length         = SZ_64K,
 242                 .type           = MT_DEVICE,
 243         }, {
 244                 .virtual        = (unsigned long)S3C_VA_TIMER,
 245                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 246                 .length         = SZ_16K,
 247                 .type           = MT_DEVICE,
 248         }, {
 249                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 250                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 251                 .length         = SZ_4K,
 252                 .type           = MT_DEVICE,
 253         }, {
 254                 .virtual        = (unsigned long)S5P_VA_SROMC,
 255                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 256                 .length         = SZ_4K,
 257                 .type           = MT_DEVICE,
 258         }, {
 259                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 260                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
 261                 .length         = SZ_4K,
 262                 .type           = MT_DEVICE,
 263         }, {
 264                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 265                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 266                 .length         = SZ_4K,
 267                 .type           = MT_DEVICE,
 268         }, {
 269                 .virtual        = (unsigned long)S5P_VA_CMU,
 270                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 271                 .length         = 144 * SZ_1K,
 272                 .type           = MT_DEVICE,
 273         }, {
 274                 .virtual        = (unsigned long)S5P_VA_PMU,
 275                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 276                 .length         = SZ_64K,
 277                 .type           = MT_DEVICE,
 278         }, {
 279                 .virtual        = (unsigned long)S3C_VA_UART,
 280                 .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
 281                 .length         = SZ_512K,
 282                 .type           = MT_DEVICE,
 283         },
 284 };
 285
 286 static struct map_desc exynos5440_iodesc0[] __initdata = {
 287         {
 288                 .virtual        = (unsigned long)S3C_VA_UART,
 289                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_UART0),
 290                 .length         = SZ_512K,
 291                 .type           = MT_DEVICE,
 292         },
 293 };
 294
 295 void exynos4_restart(char mode, const char *cmd)
 296 {
 297         __raw_writel(0x1, S5P_SWRESET);
 298 }
 299
 300 void exynos5_restart(char mode, const char *cmd)
 301 {
 302         u32 val;
 303         void __iomem *addr;
 304
 305         if (of_machine_is_compatible("samsung,exynos5250")) {
 306                 val = 0x1;
 307                 addr = EXYNOS_SWRESET;
 308         } else if (of_machine_is_compatible("samsung,exynos5440")) {
 309                 val = (0x10 << 20) | (0x1 << 16);
 310                 addr = EXYNOS5440_SWRESET;
 311         } else {
 312                 pr_err("%s: cannot support non-DT\n", __func__);
 313                 return;
 314         }
 315
 316         __raw_writel(val, addr);
 317 }
 318
 319 void __init exynos_init_late(void)
 320 {
 321         if (of_machine_is_compatible("samsung,exynos5440"))
 322                 /* to be supported later */
 323                 return;
 324
 325         exynos_pm_late_initcall();
 326 }
 327
 328 /*
 329  * exynos_map_io
 330  *
 331  * register the standard cpu IO areas
 332  */
 333
 334 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 335 {
 336         struct map_desc *iodesc = exynos_iodesc;
 337         int iodesc_sz = ARRAY_SIZE(exynos_iodesc);
 338 #if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
 339         unsigned long root = of_get_flat_dt_root();
 340
 341         /* initialize the io descriptors we need for initialization */
 342         if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) {
 343                 iodesc = exynos5440_iodesc;
 344                 iodesc_sz = ARRAY_SIZE(exynos5440_iodesc);
 345         }
 346 #endif
 347
 348         iotable_init(iodesc, iodesc_sz);
 349
 350         if (mach_desc)
 351                 iotable_init(mach_desc, size);
 352
 353         /* detect cpu id and rev. */
 354         s5p_init_cpu(S5P_VA_CHIPID);
 355
 356         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 357 }
 358
 359 static void __init exynos4_map_io(void)
 360 {
 361         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 362
 363         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 364                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 365         else
 366                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 367
 368         /* initialize device information early */
 369         exynos4_default_sdhci0();
 370         exynos4_default_sdhci1();
 371         exynos4_default_sdhci2();
 372         exynos4_default_sdhci3();
 373
 374         s3c_adc_setname("samsung-adc-v3");
 375
 376         s3c_fimc_setname(0, "exynos4-fimc");
 377         s3c_fimc_setname(1, "exynos4-fimc");
 378         s3c_fimc_setname(2, "exynos4-fimc");
 379         s3c_fimc_setname(3, "exynos4-fimc");
 380
 381         s3c_sdhci_setname(0, "exynos4-sdhci");
 382         s3c_sdhci_setname(1, "exynos4-sdhci");
 383         s3c_sdhci_setname(2, "exynos4-sdhci");
 384         s3c_sdhci_setname(3, "exynos4-sdhci");
 385
 386         /* The I2C bus controllers are directly compatible with s3c2440 */
 387         s3c_i2c0_setname("s3c2440-i2c");
 388         s3c_i2c1_setname("s3c2440-i2c");
 389         s3c_i2c2_setname("s3c2440-i2c");
 390
 391         s5p_fb_setname(0, "exynos4-fb");
 392         s5p_hdmi_setname("exynos4-hdmi");
 393
 394         s3c64xx_spi_setname("exynos4210-spi");
 395 }
 396
 397 static void __init exynos5_map_io(void)
 398 {
 399         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 400 }
 401
 402 static void __init exynos4_init_clocks(int xtal)
 403 {
 404         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 405
 406         s3c24xx_register_baseclocks(xtal);
 407         s5p_register_clocks(xtal);
 408
 409         if (soc_is_exynos4210())
 410                 exynos4210_register_clocks();
 411         else if (soc_is_exynos4212() || soc_is_exynos4412())
 412                 exynos4212_register_clocks();
 413
 414         exynos4_register_clocks();
 415         exynos4_setup_clocks();
 416 }
 417
 418 static void __init exynos5440_map_io(void)
 419 {
 420         iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 421 }
 422
 423 static void __init exynos5_init_clocks(int xtal)
 424 {
 425         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 426
 427         /* EXYNOS5440 can support only common clock framework */
 428
 429         if (soc_is_exynos5440())
 430                 return;
 431
 432 #ifdef CONFIG_SOC_EXYNOS5250
 433         s3c24xx_register_baseclocks(xtal);
 434         s5p_register_clocks(xtal);
 435
 436         exynos5_register_clocks();
 437         exynos5_setup_clocks();
 438 #endif
 439 }
 440
 441 #define COMBINER_ENABLE_SET     0x0
 442 #define COMBINER_ENABLE_CLEAR   0x4
 443 #define COMBINER_INT_STATUS     0xC
 444
 445 static DEFINE_SPINLOCK(irq_controller_lock);
 446
 447 struct combiner_chip_data {
 448         unsigned int irq_offset;
 449         unsigned int irq_mask;
 450         void __iomem *base;
 451 };
 452
 453 static struct irq_domain *combiner_irq_domain;
 454 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
 455
 456 static inline void __iomem *combiner_base(struct irq_data *data)
 457 {
 458         struct combiner_chip_data *combiner_data =
 459                 irq_data_get_irq_chip_data(data);
 460
 461         return combiner_data->base;
 462 }
 463
 464 static void combiner_mask_irq(struct irq_data *data)
 465 {
 466         u32 mask = 1 << (data->hwirq % 32);
 467
 468         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
 469 }
 470
 471 static void combiner_unmask_irq(struct irq_data *data)
 472 {
 473         u32 mask = 1 << (data->hwirq % 32);
 474
 475         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
 476 }
 477
 478 static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 479 {
 480         struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
 481         struct irq_chip *chip = irq_get_chip(irq);
 482         unsigned int cascade_irq, combiner_irq;
 483         unsigned long status;
 484
 485         chained_irq_enter(chip, desc);
 486
 487         spin_lock(&irq_controller_lock);
 488         status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
 489         spin_unlock(&irq_controller_lock);
 490         status &= chip_data->irq_mask;
 491
 492         if (status == 0)
 493                 goto out;
 494
 495         combiner_irq = __ffs(status);
 496
 497         cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
 498         if (unlikely(cascade_irq >= NR_IRQS))
 499                 do_bad_IRQ(cascade_irq, desc);
 500         else
 501                 generic_handle_irq(cascade_irq);
 502
 503  out:
 504         chained_irq_exit(chip, desc);
 505 }
 506
 507 static struct irq_chip combiner_chip = {
 508         .name           = "COMBINER",
 509         .irq_mask       = combiner_mask_irq,
 510         .irq_unmask     = combiner_unmask_irq,
 511 };
 512
 513 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
 514 {
 515         unsigned int max_nr;
 516
 517         if (soc_is_exynos5250())
 518                 max_nr = EXYNOS5_MAX_COMBINER_NR;
 519         else
 520                 max_nr = EXYNOS4_MAX_COMBINER_NR;
 521
 522         if (combiner_nr >= max_nr)
 523                 BUG();
 524         if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
 525                 BUG();
 526         irq_set_chained_handler(irq, combiner_handle_cascade_irq);
 527 }
 528
 529 static void __init combiner_init_one(unsigned int combiner_nr,
 530                                      void __iomem *base)
 531 {
 532         combiner_data[combiner_nr].base = base;
 533         combiner_data[combiner_nr].irq_offset = irq_find_mapping(
 534                 combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
 535         combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
 536
 537         /* Disable all interrupts */
 538         __raw_writel(combiner_data[combiner_nr].irq_mask,
 539                      base + COMBINER_ENABLE_CLEAR);
 540 }
 541
 542 #ifdef CONFIG_OF
 543 static int combiner_irq_domain_xlate(struct irq_domain *d,
 544                                      struct device_node *controller,
 545                                      const u32 *intspec, unsigned int intsize,
 546                                      unsigned long *out_hwirq,
 547                                      unsigned int *out_type)
 548 {
 549         if (d->of_node != controller)
 550                 return -EINVAL;
 551
 552         if (intsize < 2)
 553                 return -EINVAL;
 554
 555         *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
 556         *out_type = 0;
 557
 558         return 0;
 559 }
 560 #else
 561 static int combiner_irq_domain_xlate(struct irq_domain *d,
 562                                      struct device_node *controller,
 563                                      const u32 *intspec, unsigned int intsize,
 564                                      unsigned long *out_hwirq,
 565                                      unsigned int *out_type)
 566 {
 567         return -EINVAL;
 568 }
 569 #endif
 570
 571 static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
 572                                    irq_hw_number_t hw)
 573 {
 574         irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
 575         irq_set_chip_data(irq, &combiner_data[hw >> 3]);
 576         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 577
 578         return 0;
 579 }
 580
 581 static struct irq_domain_ops combiner_irq_domain_ops = {
 582         .xlate  = combiner_irq_domain_xlate,
 583         .map    = combiner_irq_domain_map,
 584 };
 585
 586 static void __init combiner_init(void __iomem *combiner_base,
 587                                  struct device_node *np)
 588 {
 589         int i, irq, irq_base;
 590         unsigned int max_nr, nr_irq;
 591
 592         if (np) {
 593                 if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
 594                         pr_warning("%s: number of combiners not specified, "
 595                                 "setting default as %d.\n",
 596                                 __func__, EXYNOS4_MAX_COMBINER_NR);
 597                         max_nr = EXYNOS4_MAX_COMBINER_NR;
 598                 }
 599         } else {
 600                 max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
 601                                                 EXYNOS4_MAX_COMBINER_NR;
 602         }
 603         nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
 604
 605         irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
 606         if (IS_ERR_VALUE(irq_base)) {
 607                 irq_base = COMBINER_IRQ(0, 0);
 608                 pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
 609         }
 610
 611         combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
 612                                 &combiner_irq_domain_ops, &combiner_data);
 613         if (WARN_ON(!combiner_irq_domain)) {
 614                 pr_warning("%s: irq domain init failed\n", __func__);
 615                 return;
 616         }
 617
 618         for (i = 0; i < max_nr; i++) {
 619                 combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
 620                 irq = IRQ_SPI(i);
 621 #ifdef CONFIG_OF
 622                 if (np)
 623                         irq = irq_of_parse_and_map(np, i);
 624 #endif
 625                 combiner_cascade_irq(i, irq);
 626         }
 627 }
 628
 629 #ifdef CONFIG_OF
 630 static int __init combiner_of_init(struct device_node *np,
 631                                    struct device_node *parent)
 632 {
 633         void __iomem *combiner_base;
 634
 635         combiner_base = of_iomap(np, 0);
 636         if (!combiner_base) {
 637                 pr_err("%s: failed to map combiner registers\n", __func__);
 638                 return -ENXIO;
 639         }
 640
 641         combiner_init(combiner_base, np);
 642
 643         return 0;
 644 }
 645
 646 static const struct of_device_id exynos_dt_irq_match[] = {
 647         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
 648         { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
 649         { .compatible = "samsung,exynos4210-combiner",
 650                         .data = combiner_of_init, },
 651         {},
 652 };
 653 #endif
 654
 655 void __init exynos4_init_irq(void)
 656 {
 657         unsigned int gic_bank_offset;
 658
 659         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 660
 661         if (!of_have_populated_dt())
 662                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 663 #ifdef CONFIG_OF
 664         else
 665                 of_irq_init(exynos_dt_irq_match);
 666 #endif
 667
 668         if (!of_have_populated_dt())
 669                 combiner_init(S5P_VA_COMBINER_BASE, NULL);
 670
 671         /*
 672          * The parameters of s5p_init_irq() are for VIC init.
 673          * Theses parameters should be NULL and 0 because EXYNOS4
 674          * uses GIC instead of VIC.
 675          */
 676         s5p_init_irq(NULL, 0);
 677 }
 678
 679 void __init exynos5_init_irq(void)
 680 {
 681 #ifdef CONFIG_OF
 682         of_irq_init(exynos_dt_irq_match);
 683 #endif
 684         /*
 685          * The parameters of s5p_init_irq() are for VIC init.
 686          * Theses parameters should be NULL and 0 because EXYNOS4
 687          * uses GIC instead of VIC.
 688          */
 689         if (!of_machine_is_compatible("samsung,exynos5440"))
 690                 s5p_init_irq(NULL, 0);
 691
 692         gic_arch_extn.irq_set_wake = s3c_irq_wake;
 693 }
 694
 695 struct bus_type exynos_subsys = {
 696         .name           = "exynos-core",
 697         .dev_name       = "exynos-core",
 698 };
 699
 700 static struct device exynos4_dev = {
 701         .bus    = &exynos_subsys,
 702 };
 703
 704 static int __init exynos_core_init(void)
 705 {
 706         return subsys_system_register(&exynos_subsys, NULL);
 707 }
 708 core_initcall(exynos_core_init);
 709
 710 #ifdef CONFIG_CACHE_L2X0
 711 static int __init exynos4_l2x0_cache_init(void)
 712 {
 713         int ret;
 714
 715         if (soc_is_exynos5250() || soc_is_exynos5440())
 716                 return 0;
 717
 718         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 719         if (!ret) {
 720                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 721                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 722                 return 0;
 723         }
 724
 725         if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
 726                 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
 727                 /* TAG, Data Latency Control: 2 cycles */
 728                 l2x0_saved_regs.tag_latency = 0x110;
 729
 730                 if (soc_is_exynos4212() || soc_is_exynos4412())
 731                         l2x0_saved_regs.data_latency = 0x120;
 732                 else
 733                         l2x0_saved_regs.data_latency = 0x110;
 734
 735                 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
 736                 l2x0_saved_regs.pwr_ctrl =
 737                         (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
 738
 739                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 740
 741                 __raw_writel(l2x0_saved_regs.tag_latency,
 742                                 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 743                 __raw_writel(l2x0_saved_regs.data_latency,
 744                                 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 745
 746                 /* L2X0 Prefetch Control */
 747                 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
 748                                 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 749
 750                 /* L2X0 Power Control */
 751                 __raw_writel(l2x0_saved_regs.pwr_ctrl,
 752                                 S5P_VA_L2CC + L2X0_POWER_CTRL);
 753
 754                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 755                 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
 756         }
 757
 758         l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
 759         return 0;
 760 }
 761 early_initcall(exynos4_l2x0_cache_init);
 762 #endif
 763
 764 static int __init exynos_init(void)
 765 {
 766         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 767
 768         return device_register(&exynos4_dev);
 769 }
 770
 771 /* uart registration process */
 772
 773 static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 774 {
 775         struct s3c2410_uartcfg *tcfg = cfg;
 776         u32 ucnt;
 777
 778         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 779                 tcfg->has_fracval = 1;
 780
 781         s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 782 }
 783
 784 static void __iomem *exynos_eint_base;
 785
 786 static DEFINE_SPINLOCK(eint_lock);
 787
 788 static unsigned int eint0_15_data[16];
 789
 790 static inline int exynos4_irq_to_gpio(unsigned int irq)
 791 {
 792         if (irq < IRQ_EINT(0))
 793                 return -EINVAL;
 794
 795         irq -= IRQ_EINT(0);
 796         if (irq < 8)
 797                 return EXYNOS4_GPX0(irq);
 798
 799         irq -= 8;
 800         if (irq < 8)
 801                 return EXYNOS4_GPX1(irq);
 802
 803         irq -= 8;
 804         if (irq < 8)
 805                 return EXYNOS4_GPX2(irq);
 806
 807         irq -= 8;
 808         if (irq < 8)
 809                 return EXYNOS4_GPX3(irq);
 810
 811         return -EINVAL;
 812 }
 813
 814 static inline int exynos5_irq_to_gpio(unsigned int irq)
 815 {
 816         if (irq < IRQ_EINT(0))
 817                 return -EINVAL;
 818
 819         irq -= IRQ_EINT(0);
 820         if (irq < 8)
 821                 return EXYNOS5_GPX0(irq);
 822
 823         irq -= 8;
 824         if (irq < 8)
 825                 return EXYNOS5_GPX1(irq);
 826
 827         irq -= 8;
 828         if (irq < 8)
 829                 return EXYNOS5_GPX2(irq);
 830
 831         irq -= 8;
 832         if (irq < 8)
 833                 return EXYNOS5_GPX3(irq);
 834
 835         return -EINVAL;
 836 }
 837
 838 static unsigned int exynos4_eint0_15_src_int[16] = {
 839         EXYNOS4_IRQ_EINT0,
 840         EXYNOS4_IRQ_EINT1,
 841         EXYNOS4_IRQ_EINT2,
 842         EXYNOS4_IRQ_EINT3,
 843         EXYNOS4_IRQ_EINT4,
 844         EXYNOS4_IRQ_EINT5,
 845         EXYNOS4_IRQ_EINT6,
 846         EXYNOS4_IRQ_EINT7,
 847         EXYNOS4_IRQ_EINT8,
 848         EXYNOS4_IRQ_EINT9,
 849         EXYNOS4_IRQ_EINT10,
 850         EXYNOS4_IRQ_EINT11,
 851         EXYNOS4_IRQ_EINT12,
 852         EXYNOS4_IRQ_EINT13,
 853         EXYNOS4_IRQ_EINT14,
 854         EXYNOS4_IRQ_EINT15,
 855 };
 856
 857 static unsigned int exynos5_eint0_15_src_int[16] = {
 858         EXYNOS5_IRQ_EINT0,
 859         EXYNOS5_IRQ_EINT1,
 860         EXYNOS5_IRQ_EINT2,
 861         EXYNOS5_IRQ_EINT3,
 862         EXYNOS5_IRQ_EINT4,
 863         EXYNOS5_IRQ_EINT5,
 864         EXYNOS5_IRQ_EINT6,
 865         EXYNOS5_IRQ_EINT7,
 866         EXYNOS5_IRQ_EINT8,
 867         EXYNOS5_IRQ_EINT9,
 868         EXYNOS5_IRQ_EINT10,
 869         EXYNOS5_IRQ_EINT11,
 870         EXYNOS5_IRQ_EINT12,
 871         EXYNOS5_IRQ_EINT13,
 872         EXYNOS5_IRQ_EINT14,
 873         EXYNOS5_IRQ_EINT15,
 874 };
 875 static inline void exynos_irq_eint_mask(struct irq_data *data)
 876 {
 877         u32 mask;
 878
 879         spin_lock(&eint_lock);
 880         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 881         mask |= EINT_OFFSET_BIT(data->irq);
 882         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 883         spin_unlock(&eint_lock);
 884 }
 885
 886 static void exynos_irq_eint_unmask(struct irq_data *data)
 887 {
 888         u32 mask;
 889
 890         spin_lock(&eint_lock);
 891         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 892         mask &= ~(EINT_OFFSET_BIT(data->irq));
 893         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 894         spin_unlock(&eint_lock);
 895 }
 896
 897 static inline void exynos_irq_eint_ack(struct irq_data *data)
 898 {
 899         __raw_writel(EINT_OFFSET_BIT(data->irq),
 900                      EINT_PEND(exynos_eint_base, data->irq));
 901 }
 902
 903 static void exynos_irq_eint_maskack(struct irq_data *data)
 904 {
 905         exynos_irq_eint_mask(data);
 906         exynos_irq_eint_ack(data);
 907 }
 908
 909 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 910 {
 911         int offs = EINT_OFFSET(data->irq);
 912         int shift;
 913         u32 ctrl, mask;
 914         u32 newvalue = 0;
 915
 916         switch (type) {
 917         case IRQ_TYPE_EDGE_RISING:
 918                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
 919                 break;
 920
 921         case IRQ_TYPE_EDGE_FALLING:
 922                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 923                 break;
 924
 925         case IRQ_TYPE_EDGE_BOTH:
 926                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 927                 break;
 928
 929         case IRQ_TYPE_LEVEL_LOW:
 930                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 931                 break;
 932
 933         case IRQ_TYPE_LEVEL_HIGH:
 934                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 935                 break;
 936
 937         default:
 938                 printk(KERN_ERR "No such irq type %d", type);
 939                 return -EINVAL;
 940         }
 941
 942         shift = (offs & 0x7) * 4;
 943         mask = 0x7 << shift;
 944
 945         spin_lock(&eint_lock);
 946         ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
 947         ctrl &= ~mask;
 948         ctrl |= newvalue << shift;
 949         __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
 950         spin_unlock(&eint_lock);
 951
 952         if (soc_is_exynos5250())
 953                 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 954         else
 955                 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 956
 957         return 0;
 958 }
 959
 960 static struct irq_chip exynos_irq_eint = {
 961         .name           = "exynos-eint",
 962         .irq_mask       = exynos_irq_eint_mask,
 963         .irq_unmask     = exynos_irq_eint_unmask,
 964         .irq_mask_ack   = exynos_irq_eint_maskack,
 965         .irq_ack        = exynos_irq_eint_ack,
 966         .irq_set_type   = exynos_irq_eint_set_type,
 967 #ifdef CONFIG_PM
 968         .irq_set_wake   = s3c_irqext_wake,
 969 #endif
 970 };
 971
 972 /*
 973  * exynos4_irq_demux_eint
 974  *
 975  * This function demuxes the IRQ from from EINTs 16 to 31.
 976  * It is designed to be inlined into the specific handler
 977  * s5p_irq_demux_eintX_Y.
 978  *
 979  * Each EINT pend/mask registers handle eight of them.
 980  */
 981 static inline void exynos_irq_demux_eint(unsigned int start)
 982 {
 983         unsigned int irq;
 984
 985         u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
 986         u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
 987
 988         status &= ~mask;
 989         status &= 0xff;
 990
 991         while (status) {
 992                 irq = fls(status) - 1;
 993                 generic_handle_irq(irq + start);
 994                 status &= ~(1 << irq);
 995         }
 996 }
 997
 998 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 999 {
1000         struct irq_chip *chip = irq_get_chip(irq);
1001         chained_irq_enter(chip, desc);
1002         exynos_irq_demux_eint(IRQ_EINT(16));
1003         exynos_irq_demux_eint(IRQ_EINT(24));
1004         chained_irq_exit(chip, desc);
1005 }
1006
1007 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
1008 {
1009         u32 *irq_data = irq_get_handler_data(irq);
1010         struct irq_chip *chip = irq_get_chip(irq);
1011
1012         chained_irq_enter(chip, desc);
1013         generic_handle_irq(*irq_data);
1014         chained_irq_exit(chip, desc);
1015 }
1016
1017 static int __init exynos_init_irq_eint(void)
1018 {
1019         int irq;
1020
1021 #ifdef CONFIG_PINCTRL_SAMSUNG
1022         /*
1023          * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
1024          * functionality along with support for external gpio and wakeup
1025          * interrupts. If the samsung pinctrl driver is enabled and includes
1026          * the wakeup interrupt support, then the setting up external wakeup
1027          * interrupts here can be skipped. This check here is temporary to
1028          * allow exynos4 platforms that do not use Samsung pinctrl driver to
1029          * co-exist with platforms that do. When all of the Samsung Exynos4
1030          * platforms switch over to using the pinctrl driver, the wakeup
1031          * interrupt support code here can be completely removed.
1032          */
1033         static const struct of_device_id exynos_pinctrl_ids[] = {
1034                 { .compatible = "samsung,pinctrl-exynos4210", },
1035                 { .compatible = "samsung,pinctrl-exynos4x12", },
1036         };
1037         struct device_node *pctrl_np, *wkup_np;
1038         const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
1039
1040         for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
1041                 if (of_device_is_available(pctrl_np)) {
1042                         wkup_np = of_find_compatible_node(pctrl_np, NULL,
1043                                                         wkup_compat);
1044                         if (wkup_np)
1045                                 return -ENODEV;
1046                 }
1047         }
1048 #endif
1049         if (soc_is_exynos5440())
1050                 return 0;
1051
1052         if (soc_is_exynos5250())
1053                 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
1054         else
1055                 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
1056
1057         if (exynos_eint_base == NULL) {
1058                 pr_err("unable to ioremap for EINT base address\n");
1059                 return -ENOMEM;
1060         }
1061
1062         for (irq = 0 ; irq <= 31 ; irq++) {
1063                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
1064                                          handle_level_irq);
1065                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
1066         }
1067
1068         irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
1069
1070         for (irq = 0 ; irq <= 15 ; irq++) {
1071                 eint0_15_data[irq] = IRQ_EINT(irq);
1072
1073                 if (soc_is_exynos5250()) {
1074                         irq_set_handler_data(exynos5_eint0_15_src_int[irq],
1075                                              &eint0_15_data[irq]);
1076                         irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
1077                                                 exynos_irq_eint0_15);
1078                 } else {
1079                         irq_set_handler_data(exynos4_eint0_15_src_int[irq],
1080                                              &eint0_15_data[irq]);
1081                         irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
1082                                                 exynos_irq_eint0_15);
1083                 }
1084         }
1085
1086         return 0;
1087 }
1088 arch_initcall(exynos_init_irq_eint);