1 /* linux/arch/arm/mach-exynos4/clock.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * EXYNOS4 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/err.h>
16 #include <linux/syscore_ops.h>
18 #include <plat/cpu-freq.h>
19 #include <plat/clock.h>
22 #include <plat/s5p-clock.h>
23 #include <plat/clock-clksrc.h>
24 #include <plat/exynos4.h>
28 #include <mach/regs-clock.h>
29 #include <mach/sysmmu.h>
30 #include <mach/exynos4-clock.h>
32 static struct sleep_save exynos4_clock_save[] = {
33 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
34 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
35 SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
36 SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
37 SAVE_ITEM(S5P_CLKSRC_TOP0),
38 SAVE_ITEM(S5P_CLKSRC_TOP1),
39 SAVE_ITEM(S5P_CLKSRC_CAM),
40 SAVE_ITEM(S5P_CLKSRC_TV),
41 SAVE_ITEM(S5P_CLKSRC_MFC),
42 SAVE_ITEM(S5P_CLKSRC_G3D),
43 SAVE_ITEM(S5P_CLKSRC_LCD0),
44 SAVE_ITEM(S5P_CLKSRC_MAUDIO),
45 SAVE_ITEM(S5P_CLKSRC_FSYS),
46 SAVE_ITEM(S5P_CLKSRC_PERIL0),
47 SAVE_ITEM(S5P_CLKSRC_PERIL1),
48 SAVE_ITEM(S5P_CLKDIV_CAM),
49 SAVE_ITEM(S5P_CLKDIV_TV),
50 SAVE_ITEM(S5P_CLKDIV_MFC),
51 SAVE_ITEM(S5P_CLKDIV_G3D),
52 SAVE_ITEM(S5P_CLKDIV_LCD0),
53 SAVE_ITEM(S5P_CLKDIV_MAUDIO),
54 SAVE_ITEM(S5P_CLKDIV_FSYS0),
55 SAVE_ITEM(S5P_CLKDIV_FSYS1),
56 SAVE_ITEM(S5P_CLKDIV_FSYS2),
57 SAVE_ITEM(S5P_CLKDIV_FSYS3),
58 SAVE_ITEM(S5P_CLKDIV_PERIL0),
59 SAVE_ITEM(S5P_CLKDIV_PERIL1),
60 SAVE_ITEM(S5P_CLKDIV_PERIL2),
61 SAVE_ITEM(S5P_CLKDIV_PERIL3),
62 SAVE_ITEM(S5P_CLKDIV_PERIL4),
63 SAVE_ITEM(S5P_CLKDIV_PERIL5),
64 SAVE_ITEM(S5P_CLKDIV_TOP),
65 SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
66 SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
67 SAVE_ITEM(S5P_CLKSRC_MASK_TV),
68 SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
69 SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
70 SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
71 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
72 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
73 SAVE_ITEM(S5P_CLKDIV2_RATIO),
74 SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
75 SAVE_ITEM(S5P_CLKGATE_IP_CAM),
76 SAVE_ITEM(S5P_CLKGATE_IP_TV),
77 SAVE_ITEM(S5P_CLKGATE_IP_MFC),
78 SAVE_ITEM(S5P_CLKGATE_IP_G3D),
79 SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
80 SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
81 SAVE_ITEM(S5P_CLKGATE_IP_GPS),
82 SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
83 SAVE_ITEM(S5P_CLKGATE_BLOCK),
84 SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
85 SAVE_ITEM(S5P_CLKSRC_DMC),
86 SAVE_ITEM(S5P_CLKDIV_DMC0),
87 SAVE_ITEM(S5P_CLKDIV_DMC1),
88 SAVE_ITEM(S5P_CLKGATE_IP_DMC),
89 SAVE_ITEM(S5P_CLKSRC_CPU),
90 SAVE_ITEM(S5P_CLKDIV_CPU),
91 SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
92 SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
93 SAVE_ITEM(S5P_CLKGATE_IP_CPU),
96 struct clk clk_sclk_hdmi27m = {
97 .name = "sclk_hdmi27m",
101 struct clk clk_sclk_hdmiphy = {
102 .name = "sclk_hdmiphy",
105 struct clk clk_sclk_usbphy0 = {
106 .name = "sclk_usbphy0",
110 struct clk clk_sclk_usbphy1 = {
111 .name = "sclk_usbphy1",
114 static struct clk dummy_apb_pclk = {
119 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
121 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
124 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
126 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
129 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
131 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
134 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
136 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
139 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
141 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
144 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
146 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
149 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
151 return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
154 static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
156 return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
159 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
161 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
164 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
166 return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
169 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
171 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
174 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
176 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
179 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
181 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
184 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
186 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
189 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
191 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
194 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
196 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
199 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
201 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
204 static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
206 return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
209 /* Core list of CMU_CPU side */
211 static struct clksrc_clk clk_mout_apll = {
215 .sources = &clk_src_apll,
216 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
219 struct clksrc_clk clk_sclk_apll = {
222 .parent = &clk_mout_apll.clk,
224 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
227 struct clksrc_clk clk_mout_epll = {
231 .sources = &clk_src_epll,
232 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
235 struct clksrc_clk clk_mout_mpll = {
239 .sources = &clk_src_mpll,
241 /* reg_src will be added in each SoCs' clock */
244 static struct clk *clkset_moutcore_list[] = {
245 [0] = &clk_mout_apll.clk,
246 [1] = &clk_mout_mpll.clk,
249 static struct clksrc_sources clkset_moutcore = {
250 .sources = clkset_moutcore_list,
251 .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
254 static struct clksrc_clk clk_moutcore = {
258 .sources = &clkset_moutcore,
259 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
262 static struct clksrc_clk clk_coreclk = {
265 .parent = &clk_moutcore.clk,
267 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
270 static struct clksrc_clk clk_armclk = {
273 .parent = &clk_coreclk.clk,
277 static struct clksrc_clk clk_aclk_corem0 = {
279 .name = "aclk_corem0",
280 .parent = &clk_coreclk.clk,
282 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
285 static struct clksrc_clk clk_aclk_cores = {
287 .name = "aclk_cores",
288 .parent = &clk_coreclk.clk,
290 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
293 static struct clksrc_clk clk_aclk_corem1 = {
295 .name = "aclk_corem1",
296 .parent = &clk_coreclk.clk,
298 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
301 static struct clksrc_clk clk_periphclk = {
304 .parent = &clk_coreclk.clk,
306 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
309 /* Core list of CMU_CORE side */
311 struct clk *clkset_corebus_list[] = {
312 [0] = &clk_mout_mpll.clk,
313 [1] = &clk_sclk_apll.clk,
316 struct clksrc_sources clkset_mout_corebus = {
317 .sources = clkset_corebus_list,
318 .nr_sources = ARRAY_SIZE(clkset_corebus_list),
321 static struct clksrc_clk clk_mout_corebus = {
323 .name = "mout_corebus",
325 .sources = &clkset_mout_corebus,
326 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
329 static struct clksrc_clk clk_sclk_dmc = {
332 .parent = &clk_mout_corebus.clk,
334 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
337 static struct clksrc_clk clk_aclk_cored = {
339 .name = "aclk_cored",
340 .parent = &clk_sclk_dmc.clk,
342 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
345 static struct clksrc_clk clk_aclk_corep = {
347 .name = "aclk_corep",
348 .parent = &clk_aclk_cored.clk,
350 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
353 static struct clksrc_clk clk_aclk_acp = {
356 .parent = &clk_mout_corebus.clk,
358 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
361 static struct clksrc_clk clk_pclk_acp = {
364 .parent = &clk_aclk_acp.clk,
366 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
369 /* Core list of CMU_TOP side */
371 struct clk *clkset_aclk_top_list[] = {
372 [0] = &clk_mout_mpll.clk,
373 [1] = &clk_sclk_apll.clk,
376 struct clksrc_sources clkset_aclk = {
377 .sources = clkset_aclk_top_list,
378 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
381 static struct clksrc_clk clk_aclk_200 = {
385 .sources = &clkset_aclk,
386 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
387 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
390 static struct clksrc_clk clk_aclk_100 = {
394 .sources = &clkset_aclk,
395 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
396 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
399 static struct clksrc_clk clk_aclk_160 = {
403 .sources = &clkset_aclk,
404 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
405 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
408 struct clksrc_clk clk_aclk_133 = {
412 .sources = &clkset_aclk,
413 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
414 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
417 static struct clk *clkset_vpllsrc_list[] = {
419 [1] = &clk_sclk_hdmi27m,
422 static struct clksrc_sources clkset_vpllsrc = {
423 .sources = clkset_vpllsrc_list,
424 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
427 static struct clksrc_clk clk_vpllsrc = {
430 .enable = exynos4_clksrc_mask_top_ctrl,
433 .sources = &clkset_vpllsrc,
434 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
437 static struct clk *clkset_sclk_vpll_list[] = {
438 [0] = &clk_vpllsrc.clk,
439 [1] = &clk_fout_vpll,
442 static struct clksrc_sources clkset_sclk_vpll = {
443 .sources = clkset_sclk_vpll_list,
444 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
447 struct clksrc_clk clk_sclk_vpll = {
451 .sources = &clkset_sclk_vpll,
452 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
455 static struct clk init_clocks_off[] = {
458 .parent = &clk_aclk_100.clk,
459 .enable = exynos4_clk_ip_peril_ctrl,
463 .devname = "s5p-mipi-csis.0",
464 .enable = exynos4_clk_ip_cam_ctrl,
468 .devname = "s5p-mipi-csis.1",
469 .enable = exynos4_clk_ip_cam_ctrl,
473 .devname = "exynos4-fimc.0",
474 .enable = exynos4_clk_ip_cam_ctrl,
478 .devname = "exynos4-fimc.1",
479 .enable = exynos4_clk_ip_cam_ctrl,
483 .devname = "exynos4-fimc.2",
484 .enable = exynos4_clk_ip_cam_ctrl,
488 .devname = "exynos4-fimc.3",
489 .enable = exynos4_clk_ip_cam_ctrl,
493 .devname = "exynos4-fb.0",
494 .enable = exynos4_clk_ip_lcd0_ctrl,
498 .devname = "s3c-sdhci.0",
499 .parent = &clk_aclk_133.clk,
500 .enable = exynos4_clk_ip_fsys_ctrl,
504 .devname = "s3c-sdhci.1",
505 .parent = &clk_aclk_133.clk,
506 .enable = exynos4_clk_ip_fsys_ctrl,
510 .devname = "s3c-sdhci.2",
511 .parent = &clk_aclk_133.clk,
512 .enable = exynos4_clk_ip_fsys_ctrl,
516 .devname = "s3c-sdhci.3",
517 .parent = &clk_aclk_133.clk,
518 .enable = exynos4_clk_ip_fsys_ctrl,
522 .parent = &clk_aclk_133.clk,
523 .enable = exynos4_clk_ip_fsys_ctrl,
527 .devname = "s5p-sdo",
528 .enable = exynos4_clk_ip_tv_ctrl,
532 .devname = "s5p-mixer",
533 .enable = exynos4_clk_ip_tv_ctrl,
537 .devname = "s5p-mixer",
538 .enable = exynos4_clk_ip_tv_ctrl,
542 .devname = "exynos4-hdmi",
543 .enable = exynos4_clk_ip_tv_ctrl,
547 .devname = "exynos4-hdmi",
548 .enable = exynos4_clk_hdmiphy_ctrl,
552 .devname = "s5p-sdo",
553 .enable = exynos4_clk_dac_ctrl,
557 .devname = "dma-pl330.0",
558 .enable = exynos4_clk_ip_fsys_ctrl,
562 .devname = "dma-pl330.1",
563 .enable = exynos4_clk_ip_fsys_ctrl,
567 .enable = exynos4_clk_ip_peril_ctrl,
568 .ctrlbit = (1 << 15),
571 .enable = exynos4_clk_ip_perir_ctrl,
572 .ctrlbit = (1 << 16),
575 .enable = exynos4_clk_ip_perir_ctrl,
576 .ctrlbit = (1 << 15),
579 .parent = &clk_aclk_100.clk,
580 .enable = exynos4_clk_ip_perir_ctrl,
581 .ctrlbit = (1 << 14),
584 .enable = exynos4_clk_ip_fsys_ctrl ,
585 .ctrlbit = (1 << 12),
588 .enable = exynos4_clk_ip_fsys_ctrl,
589 .ctrlbit = (1 << 13),
592 .devname = "s3c64xx-spi.0",
593 .enable = exynos4_clk_ip_peril_ctrl,
594 .ctrlbit = (1 << 16),
597 .devname = "s3c64xx-spi.1",
598 .enable = exynos4_clk_ip_peril_ctrl,
599 .ctrlbit = (1 << 17),
602 .devname = "s3c64xx-spi.2",
603 .enable = exynos4_clk_ip_peril_ctrl,
604 .ctrlbit = (1 << 18),
607 .devname = "samsung-i2s.0",
608 .enable = exynos4_clk_ip_peril_ctrl,
609 .ctrlbit = (1 << 19),
612 .devname = "samsung-i2s.1",
613 .enable = exynos4_clk_ip_peril_ctrl,
614 .ctrlbit = (1 << 20),
617 .devname = "samsung-i2s.2",
618 .enable = exynos4_clk_ip_peril_ctrl,
619 .ctrlbit = (1 << 21),
622 .devname = "samsung-ac97",
623 .enable = exynos4_clk_ip_peril_ctrl,
624 .ctrlbit = (1 << 27),
627 .enable = exynos4_clk_ip_image_ctrl,
631 .devname = "s5p-mfc",
632 .enable = exynos4_clk_ip_mfc_ctrl,
636 .devname = "s3c2440-i2c.0",
637 .parent = &clk_aclk_100.clk,
638 .enable = exynos4_clk_ip_peril_ctrl,
642 .devname = "s3c2440-i2c.1",
643 .parent = &clk_aclk_100.clk,
644 .enable = exynos4_clk_ip_peril_ctrl,
648 .devname = "s3c2440-i2c.2",
649 .parent = &clk_aclk_100.clk,
650 .enable = exynos4_clk_ip_peril_ctrl,
654 .devname = "s3c2440-i2c.3",
655 .parent = &clk_aclk_100.clk,
656 .enable = exynos4_clk_ip_peril_ctrl,
660 .devname = "s3c2440-i2c.4",
661 .parent = &clk_aclk_100.clk,
662 .enable = exynos4_clk_ip_peril_ctrl,
663 .ctrlbit = (1 << 10),
666 .devname = "s3c2440-i2c.5",
667 .parent = &clk_aclk_100.clk,
668 .enable = exynos4_clk_ip_peril_ctrl,
669 .ctrlbit = (1 << 11),
672 .devname = "s3c2440-i2c.6",
673 .parent = &clk_aclk_100.clk,
674 .enable = exynos4_clk_ip_peril_ctrl,
675 .ctrlbit = (1 << 12),
678 .devname = "s3c2440-i2c.7",
679 .parent = &clk_aclk_100.clk,
680 .enable = exynos4_clk_ip_peril_ctrl,
681 .ctrlbit = (1 << 13),
684 .devname = "s3c2440-hdmiphy-i2c",
685 .parent = &clk_aclk_100.clk,
686 .enable = exynos4_clk_ip_peril_ctrl,
687 .ctrlbit = (1 << 14),
689 .name = "SYSMMU_MDMA",
690 .enable = exynos4_clk_ip_image_ctrl,
693 .name = "SYSMMU_FIMC0",
694 .enable = exynos4_clk_ip_cam_ctrl,
697 .name = "SYSMMU_FIMC1",
698 .enable = exynos4_clk_ip_cam_ctrl,
701 .name = "SYSMMU_FIMC2",
702 .enable = exynos4_clk_ip_cam_ctrl,
705 .name = "SYSMMU_FIMC3",
706 .enable = exynos4_clk_ip_cam_ctrl,
707 .ctrlbit = (1 << 10),
709 .name = "SYSMMU_JPEG",
710 .enable = exynos4_clk_ip_cam_ctrl,
711 .ctrlbit = (1 << 11),
713 .name = "SYSMMU_FIMD0",
714 .enable = exynos4_clk_ip_lcd0_ctrl,
717 .name = "SYSMMU_FIMD1",
718 .enable = exynos4_clk_ip_lcd1_ctrl,
721 .name = "SYSMMU_PCIe",
722 .enable = exynos4_clk_ip_fsys_ctrl,
723 .ctrlbit = (1 << 18),
725 .name = "SYSMMU_G2D",
726 .enable = exynos4_clk_ip_image_ctrl,
729 .name = "SYSMMU_ROTATOR",
730 .enable = exynos4_clk_ip_image_ctrl,
734 .enable = exynos4_clk_ip_tv_ctrl,
737 .name = "SYSMMU_MFC_L",
738 .enable = exynos4_clk_ip_mfc_ctrl,
741 .name = "SYSMMU_MFC_R",
742 .enable = exynos4_clk_ip_mfc_ctrl,
747 static struct clk init_clocks[] = {
750 .devname = "s5pv210-uart.0",
751 .enable = exynos4_clk_ip_peril_ctrl,
755 .devname = "s5pv210-uart.1",
756 .enable = exynos4_clk_ip_peril_ctrl,
760 .devname = "s5pv210-uart.2",
761 .enable = exynos4_clk_ip_peril_ctrl,
765 .devname = "s5pv210-uart.3",
766 .enable = exynos4_clk_ip_peril_ctrl,
770 .devname = "s5pv210-uart.4",
771 .enable = exynos4_clk_ip_peril_ctrl,
775 .devname = "s5pv210-uart.5",
776 .enable = exynos4_clk_ip_peril_ctrl,
781 struct clk *clkset_group_list[] = {
782 [0] = &clk_ext_xtal_mux,
784 [2] = &clk_sclk_hdmi27m,
785 [3] = &clk_sclk_usbphy0,
786 [4] = &clk_sclk_usbphy1,
787 [5] = &clk_sclk_hdmiphy,
788 [6] = &clk_mout_mpll.clk,
789 [7] = &clk_mout_epll.clk,
790 [8] = &clk_sclk_vpll.clk,
793 struct clksrc_sources clkset_group = {
794 .sources = clkset_group_list,
795 .nr_sources = ARRAY_SIZE(clkset_group_list),
798 static struct clk *clkset_mout_g2d0_list[] = {
799 [0] = &clk_mout_mpll.clk,
800 [1] = &clk_sclk_apll.clk,
803 static struct clksrc_sources clkset_mout_g2d0 = {
804 .sources = clkset_mout_g2d0_list,
805 .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
808 static struct clksrc_clk clk_mout_g2d0 = {
812 .sources = &clkset_mout_g2d0,
813 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
816 static struct clk *clkset_mout_g2d1_list[] = {
817 [0] = &clk_mout_epll.clk,
818 [1] = &clk_sclk_vpll.clk,
821 static struct clksrc_sources clkset_mout_g2d1 = {
822 .sources = clkset_mout_g2d1_list,
823 .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
826 static struct clksrc_clk clk_mout_g2d1 = {
830 .sources = &clkset_mout_g2d1,
831 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
834 static struct clk *clkset_mout_g2d_list[] = {
835 [0] = &clk_mout_g2d0.clk,
836 [1] = &clk_mout_g2d1.clk,
839 static struct clksrc_sources clkset_mout_g2d = {
840 .sources = clkset_mout_g2d_list,
841 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
844 static struct clk *clkset_mout_mfc0_list[] = {
845 [0] = &clk_mout_mpll.clk,
846 [1] = &clk_sclk_apll.clk,
849 static struct clksrc_sources clkset_mout_mfc0 = {
850 .sources = clkset_mout_mfc0_list,
851 .nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list),
854 static struct clksrc_clk clk_mout_mfc0 = {
858 .sources = &clkset_mout_mfc0,
859 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
862 static struct clk *clkset_mout_mfc1_list[] = {
863 [0] = &clk_mout_epll.clk,
864 [1] = &clk_sclk_vpll.clk,
867 static struct clksrc_sources clkset_mout_mfc1 = {
868 .sources = clkset_mout_mfc1_list,
869 .nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list),
872 static struct clksrc_clk clk_mout_mfc1 = {
876 .sources = &clkset_mout_mfc1,
877 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
880 static struct clk *clkset_mout_mfc_list[] = {
881 [0] = &clk_mout_mfc0.clk,
882 [1] = &clk_mout_mfc1.clk,
885 static struct clksrc_sources clkset_mout_mfc = {
886 .sources = clkset_mout_mfc_list,
887 .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list),
890 static struct clk *clkset_sclk_dac_list[] = {
891 [0] = &clk_sclk_vpll.clk,
892 [1] = &clk_sclk_hdmiphy,
895 static struct clksrc_sources clkset_sclk_dac = {
896 .sources = clkset_sclk_dac_list,
897 .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
900 static struct clksrc_clk clk_sclk_dac = {
903 .enable = exynos4_clksrc_mask_tv_ctrl,
906 .sources = &clkset_sclk_dac,
907 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
910 static struct clksrc_clk clk_sclk_pixel = {
912 .name = "sclk_pixel",
913 .parent = &clk_sclk_vpll.clk,
915 .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
918 static struct clk *clkset_sclk_hdmi_list[] = {
919 [0] = &clk_sclk_pixel.clk,
920 [1] = &clk_sclk_hdmiphy,
923 static struct clksrc_sources clkset_sclk_hdmi = {
924 .sources = clkset_sclk_hdmi_list,
925 .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
928 static struct clksrc_clk clk_sclk_hdmi = {
931 .enable = exynos4_clksrc_mask_tv_ctrl,
934 .sources = &clkset_sclk_hdmi,
935 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
938 static struct clk *clkset_sclk_mixer_list[] = {
939 [0] = &clk_sclk_dac.clk,
940 [1] = &clk_sclk_hdmi.clk,
943 static struct clksrc_sources clkset_sclk_mixer = {
944 .sources = clkset_sclk_mixer_list,
945 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
948 static struct clksrc_clk clk_sclk_mixer = {
950 .name = "sclk_mixer",
951 .enable = exynos4_clksrc_mask_tv_ctrl,
954 .sources = &clkset_sclk_mixer,
955 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
958 static struct clksrc_clk *sclk_tv[] = {
965 static struct clksrc_clk clk_dout_mmc0 = {
969 .sources = &clkset_group,
970 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
971 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
974 static struct clksrc_clk clk_dout_mmc1 = {
978 .sources = &clkset_group,
979 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
980 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
983 static struct clksrc_clk clk_dout_mmc2 = {
987 .sources = &clkset_group,
988 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
989 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
992 static struct clksrc_clk clk_dout_mmc3 = {
996 .sources = &clkset_group,
997 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
998 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1001 static struct clksrc_clk clk_dout_mmc4 = {
1003 .name = "dout_mmc4",
1005 .sources = &clkset_group,
1006 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
1007 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1010 static struct clksrc_clk clksrcs[] = {
1014 .devname = "s5pv210-uart.0",
1015 .enable = exynos4_clksrc_mask_peril0_ctrl,
1016 .ctrlbit = (1 << 0),
1018 .sources = &clkset_group,
1019 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1020 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1024 .devname = "s5pv210-uart.1",
1025 .enable = exynos4_clksrc_mask_peril0_ctrl,
1026 .ctrlbit = (1 << 4),
1028 .sources = &clkset_group,
1029 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1030 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1034 .devname = "s5pv210-uart.2",
1035 .enable = exynos4_clksrc_mask_peril0_ctrl,
1036 .ctrlbit = (1 << 8),
1038 .sources = &clkset_group,
1039 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1040 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1044 .devname = "s5pv210-uart.3",
1045 .enable = exynos4_clksrc_mask_peril0_ctrl,
1046 .ctrlbit = (1 << 12),
1048 .sources = &clkset_group,
1049 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1050 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1054 .enable = exynos4_clksrc_mask_peril0_ctrl,
1055 .ctrlbit = (1 << 24),
1057 .sources = &clkset_group,
1058 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1059 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1062 .name = "sclk_csis",
1063 .devname = "s5p-mipi-csis.0",
1064 .enable = exynos4_clksrc_mask_cam_ctrl,
1065 .ctrlbit = (1 << 24),
1067 .sources = &clkset_group,
1068 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
1069 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
1072 .name = "sclk_csis",
1073 .devname = "s5p-mipi-csis.1",
1074 .enable = exynos4_clksrc_mask_cam_ctrl,
1075 .ctrlbit = (1 << 28),
1077 .sources = &clkset_group,
1078 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
1079 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
1082 .name = "sclk_cam0",
1083 .enable = exynos4_clksrc_mask_cam_ctrl,
1084 .ctrlbit = (1 << 16),
1086 .sources = &clkset_group,
1087 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
1088 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
1091 .name = "sclk_cam1",
1092 .enable = exynos4_clksrc_mask_cam_ctrl,
1093 .ctrlbit = (1 << 20),
1095 .sources = &clkset_group,
1096 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
1097 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
1100 .name = "sclk_fimc",
1101 .devname = "exynos4-fimc.0",
1102 .enable = exynos4_clksrc_mask_cam_ctrl,
1103 .ctrlbit = (1 << 0),
1105 .sources = &clkset_group,
1106 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
1107 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
1110 .name = "sclk_fimc",
1111 .devname = "exynos4-fimc.1",
1112 .enable = exynos4_clksrc_mask_cam_ctrl,
1113 .ctrlbit = (1 << 4),
1115 .sources = &clkset_group,
1116 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
1117 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
1120 .name = "sclk_fimc",
1121 .devname = "exynos4-fimc.2",
1122 .enable = exynos4_clksrc_mask_cam_ctrl,
1123 .ctrlbit = (1 << 8),
1125 .sources = &clkset_group,
1126 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
1127 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
1130 .name = "sclk_fimc",
1131 .devname = "exynos4-fimc.3",
1132 .enable = exynos4_clksrc_mask_cam_ctrl,
1133 .ctrlbit = (1 << 12),
1135 .sources = &clkset_group,
1136 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
1137 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
1140 .name = "sclk_fimd",
1141 .devname = "exynos4-fb.0",
1142 .enable = exynos4_clksrc_mask_lcd0_ctrl,
1143 .ctrlbit = (1 << 0),
1145 .sources = &clkset_group,
1146 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
1147 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
1151 .devname = "s3c64xx-spi.0",
1152 .enable = exynos4_clksrc_mask_peril1_ctrl,
1153 .ctrlbit = (1 << 16),
1155 .sources = &clkset_group,
1156 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1157 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1161 .devname = "s3c64xx-spi.1",
1162 .enable = exynos4_clksrc_mask_peril1_ctrl,
1163 .ctrlbit = (1 << 20),
1165 .sources = &clkset_group,
1166 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1167 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1171 .devname = "s3c64xx-spi.2",
1172 .enable = exynos4_clksrc_mask_peril1_ctrl,
1173 .ctrlbit = (1 << 24),
1175 .sources = &clkset_group,
1176 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1177 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1180 .name = "sclk_fimg2d",
1182 .sources = &clkset_mout_g2d,
1183 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1184 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1188 .devname = "s5p-mfc",
1190 .sources = &clkset_mout_mfc,
1191 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
1192 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1196 .devname = "s3c-sdhci.0",
1197 .parent = &clk_dout_mmc0.clk,
1198 .enable = exynos4_clksrc_mask_fsys_ctrl,
1199 .ctrlbit = (1 << 0),
1201 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1205 .devname = "s3c-sdhci.1",
1206 .parent = &clk_dout_mmc1.clk,
1207 .enable = exynos4_clksrc_mask_fsys_ctrl,
1208 .ctrlbit = (1 << 4),
1210 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1214 .devname = "s3c-sdhci.2",
1215 .parent = &clk_dout_mmc2.clk,
1216 .enable = exynos4_clksrc_mask_fsys_ctrl,
1217 .ctrlbit = (1 << 8),
1219 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1223 .devname = "s3c-sdhci.3",
1224 .parent = &clk_dout_mmc3.clk,
1225 .enable = exynos4_clksrc_mask_fsys_ctrl,
1226 .ctrlbit = (1 << 12),
1228 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1231 .name = "sclk_dwmmc",
1232 .parent = &clk_dout_mmc4.clk,
1233 .enable = exynos4_clksrc_mask_fsys_ctrl,
1234 .ctrlbit = (1 << 16),
1236 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1240 /* Clock initialization code */
1241 static struct clksrc_clk *sysclks[] = {
1274 static int xtal_rate;
1276 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1278 if (soc_is_exynos4210())
1279 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
1281 else if (soc_is_exynos4212() || soc_is_exynos4412())
1282 return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
1287 static struct clk_ops exynos4_fout_apll_ops = {
1288 .get_rate = exynos4_fout_apll_get_rate,
1291 static u32 vpll_div[][8] = {
1292 { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
1293 { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1296 static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1301 static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1303 unsigned int vpll_con0, vpll_con1 = 0;
1306 /* Return if nothing changed */
1307 if (clk->rate == rate)
1310 vpll_con0 = __raw_readl(S5P_VPLL_CON0);
1311 vpll_con0 &= ~(0x1 << 27 | \
1312 PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1313 PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1314 PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1316 vpll_con1 = __raw_readl(S5P_VPLL_CON1);
1317 vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
1318 PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1319 PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1321 for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
1322 if (vpll_div[i][0] == rate) {
1323 vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1324 vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1325 vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1326 vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1327 vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1328 vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1329 vpll_con0 |= vpll_div[i][7] << 27;
1334 if (i == ARRAY_SIZE(vpll_div)) {
1335 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1340 __raw_writel(vpll_con0, S5P_VPLL_CON0);
1341 __raw_writel(vpll_con1, S5P_VPLL_CON1);
1343 /* Wait for VPLL lock */
1344 while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1351 static struct clk_ops exynos4_vpll_ops = {
1352 .get_rate = exynos4_vpll_get_rate,
1353 .set_rate = exynos4_vpll_set_rate,
1356 void __init_or_cpufreq exynos4_setup_clocks(void)
1358 struct clk *xtal_clk;
1359 unsigned long apll = 0;
1360 unsigned long mpll = 0;
1361 unsigned long epll = 0;
1362 unsigned long vpll = 0;
1363 unsigned long vpllsrc;
1365 unsigned long armclk;
1366 unsigned long sclk_dmc;
1367 unsigned long aclk_200;
1368 unsigned long aclk_100;
1369 unsigned long aclk_160;
1370 unsigned long aclk_133;
1373 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1375 xtal_clk = clk_get(NULL, "xtal");
1376 BUG_ON(IS_ERR(xtal_clk));
1378 xtal = clk_get_rate(xtal_clk);
1384 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1386 if (soc_is_exynos4210()) {
1387 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
1389 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
1391 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1392 __raw_readl(S5P_EPLL_CON1), pll_4600);
1394 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1395 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1396 __raw_readl(S5P_VPLL_CON1), pll_4650c);
1397 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1398 apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
1399 mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
1400 epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
1401 __raw_readl(S5P_EPLL_CON1));
1403 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1404 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1405 __raw_readl(S5P_VPLL_CON1));
1410 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1411 clk_fout_mpll.rate = mpll;
1412 clk_fout_epll.rate = epll;
1413 clk_fout_vpll.ops = &exynos4_vpll_ops;
1414 clk_fout_vpll.rate = vpll;
1416 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1417 apll, mpll, epll, vpll);
1419 armclk = clk_get_rate(&clk_armclk.clk);
1420 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1422 aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1423 aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1424 aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1425 aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1427 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1428 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1429 armclk, sclk_dmc, aclk_200,
1430 aclk_100, aclk_160, aclk_133);
1432 clk_f.rate = armclk;
1433 clk_h.rate = sclk_dmc;
1434 clk_p.rate = aclk_100;
1436 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1437 s3c_set_clksrc(&clksrcs[ptr], true);
1440 static struct clk *clks[] __initdata = {
1447 #ifdef CONFIG_PM_SLEEP
1448 static int exynos4_clock_suspend(void)
1450 s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1454 static void exynos4_clock_resume(void)
1456 s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1460 #define exynos4_clock_suspend NULL
1461 #define exynos4_clock_resume NULL
1464 struct syscore_ops exynos4_clock_syscore_ops = {
1465 .suspend = exynos4_clock_suspend,
1466 .resume = exynos4_clock_resume,
1469 void __init exynos4_register_clocks(void)
1473 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1475 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1476 s3c_register_clksrc(sysclks[ptr], 1);
1478 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1479 s3c_register_clksrc(sclk_tv[ptr], 1);
1481 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1482 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1484 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1485 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1487 register_syscore_ops(&exynos4_clock_syscore_ops);
1488 s3c24xx_register_clock(&dummy_apb_pclk);