2 * arch/arm/mach-dove/pcie.c
4 * PCIe functions for Marvell Dove 88AP510 SoC
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <video/vga.h>
14 #include <asm/mach/pci.h>
15 #include <asm/mach/arch.h>
16 #include <asm/setup.h>
17 #include <asm/delay.h>
18 #include <plat/pcie.h>
19 #include <mach/irqs.h>
20 #include <mach/bridge-regs.h>
21 #include <plat/addr-map.h>
29 char mem_space_name[16];
33 static struct pcie_port pcie_port[2];
34 static int num_pcie_ports;
37 static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
41 if (nr >= num_pcie_ports)
45 sys->private_data = pp;
46 pp->root_bus_nr = sys->busnr;
49 * Generic PCIe unit setup.
51 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
53 orion_pcie_setup(pp->base);
56 pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE);
58 pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE);
63 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
64 "PCIe %d MEM", pp->index);
65 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
66 pp->res.name = pp->mem_space_name;
68 pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE;
69 pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1;
71 pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE;
72 pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1;
74 pp->res.flags = IORESOURCE_MEM;
75 if (request_resource(&iomem_resource, &pp->res))
76 panic("Request PCIe Memory resource failed\n");
77 pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
82 static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
85 * Don't go out when trying to access nonexisting devices
88 if (bus == pp->root_bus_nr && dev > 1)
94 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
97 struct pci_sys_data *sys = bus->sysdata;
98 struct pcie_port *pp = sys->private_data;
102 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
104 return PCIBIOS_DEVICE_NOT_FOUND;
107 spin_lock_irqsave(&pp->conf_lock, flags);
108 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
109 spin_unlock_irqrestore(&pp->conf_lock, flags);
114 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
115 int where, int size, u32 val)
117 struct pci_sys_data *sys = bus->sysdata;
118 struct pcie_port *pp = sys->private_data;
122 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
123 return PCIBIOS_DEVICE_NOT_FOUND;
125 spin_lock_irqsave(&pp->conf_lock, flags);
126 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
127 spin_unlock_irqrestore(&pp->conf_lock, flags);
132 static struct pci_ops pcie_ops = {
133 .read = pcie_rd_conf,
134 .write = pcie_wr_conf,
137 static void __devinit rc_pci_fixup(struct pci_dev *dev)
140 * Prevent enumeration of root complex.
142 if (dev->bus->parent == NULL && dev->devfn == 0) {
145 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
146 dev->resource[i].start = 0;
147 dev->resource[i].end = 0;
148 dev->resource[i].flags = 0;
152 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
154 static struct pci_bus __init *
155 dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
159 if (nr < num_pcie_ports) {
160 bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
170 static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
172 struct pci_sys_data *sys = dev->sysdata;
173 struct pcie_port *pp = sys->private_data;
175 return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
178 static struct hw_pci dove_pci __initdata = {
180 .setup = dove_pcie_setup,
181 .scan = dove_pcie_scan_bus,
182 .map_irq = dove_pcie_map_irq,
185 static void __init add_pcie_port(int index, void __iomem *base)
187 printk(KERN_INFO "Dove PCIe port %d: ", index);
189 if (orion_pcie_link_up(base)) {
190 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
192 printk(KERN_INFO "link up\n");
195 pp->root_bus_nr = -1;
197 spin_lock_init(&pp->conf_lock);
198 memset(&pp->res, 0, sizeof(pp->res));
200 printk(KERN_INFO "link down, ignoring\n");
204 void __init dove_pcie_init(int init_port0, int init_port1)
206 vga_base = DOVE_PCIE0_MEM_PHYS_BASE;
209 add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
212 add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);
214 pci_common_init(&dove_pci);