2 * arch/arm/mach-dove/irq.c
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/irq.h>
14 #include <linux/gpio.h>
16 #include <asm/mach/arch.h>
18 #include <asm/mach/irq.h>
20 #include <mach/bridge-regs.h>
23 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
26 BUG_ON(irq < IRQ_DOVE_GPIO_0_7 || irq > IRQ_DOVE_HIGH_GPIO);
28 irqoff = irq <= IRQ_DOVE_GPIO_16_23 ? irq - IRQ_DOVE_GPIO_0_7 :
29 3 + irq - IRQ_DOVE_GPIO_24_31;
31 orion_gpio_irq_handler(irqoff << 3);
32 if (irq == IRQ_DOVE_HIGH_GPIO) {
33 orion_gpio_irq_handler(40);
34 orion_gpio_irq_handler(48);
35 orion_gpio_irq_handler(56);
39 static void pmu_irq_mask(struct irq_data *d)
41 int pin = irq_to_pmu(d->irq);
44 u = readl(PMU_INTERRUPT_MASK);
45 u &= ~(1 << (pin & 31));
46 writel(u, PMU_INTERRUPT_MASK);
49 static void pmu_irq_unmask(struct irq_data *d)
51 int pin = irq_to_pmu(d->irq);
54 u = readl(PMU_INTERRUPT_MASK);
56 writel(u, PMU_INTERRUPT_MASK);
59 static void pmu_irq_ack(struct irq_data *d)
61 int pin = irq_to_pmu(d->irq);
65 * The PMU mask register is not RW0C: it is RW. This means that
66 * the bits take whatever value is written to them; if you write
67 * a '1', you will set the interrupt.
69 * Unfortunately this means there is NO race free way to clear
72 * So, let's structure the code so that the window is as small as
75 u = ~(1 << (pin & 31));
76 u &= readl_relaxed(PMU_INTERRUPT_CAUSE);
77 writel_relaxed(u, PMU_INTERRUPT_CAUSE);
80 static struct irq_chip pmu_irq_chip = {
82 .irq_mask = pmu_irq_mask,
83 .irq_unmask = pmu_irq_unmask,
84 .irq_ack = pmu_irq_ack,
87 static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
89 unsigned long cause = readl(PMU_INTERRUPT_CAUSE);
91 cause &= readl(PMU_INTERRUPT_MASK);
93 do_bad_IRQ(irq, desc);
97 for (irq = 0; irq < NR_PMU_IRQS; irq++) {
98 if (!(cause & (1 << irq)))
100 irq = pmu_to_irq(irq);
101 generic_handle_irq(irq);
105 void __init dove_init_irq(void)
109 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
110 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
113 * Initialize gpiolib for GPIOs 0-71.
115 orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
116 IRQ_DOVE_GPIO_START);
117 irq_set_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
118 irq_set_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
119 irq_set_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
120 irq_set_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
122 orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
123 IRQ_DOVE_GPIO_START + 32);
124 irq_set_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
126 orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,
127 IRQ_DOVE_GPIO_START + 64);
130 * Mask and clear PMU interrupts
132 writel(0, PMU_INTERRUPT_MASK);
133 writel(0, PMU_INTERRUPT_CAUSE);
135 for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
136 irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq);
137 irq_set_status_flags(i, IRQ_LEVEL);
138 set_irq_flags(i, IRQF_VALID);
140 irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);