2 * TI DA850/OMAP-L138 chip specific setup
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
14 #include <linux/init.h>
15 #include <linux/clk.h>
16 #include <linux/platform_device.h>
17 #include <linux/cpufreq.h>
18 #include <linux/regulator/consumer.h>
20 #include <asm/mach/map.h>
23 #include <mach/irqs.h>
24 #include <mach/cputype.h>
25 #include <mach/common.h>
26 #include <mach/time.h>
27 #include <mach/da8xx.h>
28 #include <mach/cpufreq.h>
30 #include <mach/gpio.h>
35 /* SoC specific clock flags */
36 #define DA850_CLK_ASYNC3 BIT(16)
38 #define DA850_PLL1_BASE 0x01e1a000
39 #define DA850_TIMER64P2_BASE 0x01f0c000
40 #define DA850_TIMER64P3_BASE 0x01f0d000
42 #define DA850_REF_FREQ 24000000
44 #define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
45 #define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
46 #define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
48 static int da850_set_armrate(struct clk *clk, unsigned long rate);
49 static int da850_round_armrate(struct clk *clk, unsigned long rate);
50 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
52 static struct pll_data pll0_data = {
54 .phys_base = DA8XX_PLL0_BASE,
55 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
58 static struct clk ref_clk = {
60 .rate = DA850_REF_FREQ,
63 static struct clk pll0_clk = {
66 .pll_data = &pll0_data,
68 .set_rate = da850_set_pll0rate,
71 static struct clk pll0_aux_clk = {
72 .name = "pll0_aux_clk",
74 .flags = CLK_PLL | PRE_PLL,
77 static struct clk pll0_sysclk2 = {
78 .name = "pll0_sysclk2",
84 static struct clk pll0_sysclk3 = {
85 .name = "pll0_sysclk3",
89 .set_rate = davinci_set_sysclk_rate,
93 static struct clk pll0_sysclk4 = {
94 .name = "pll0_sysclk4",
100 static struct clk pll0_sysclk5 = {
101 .name = "pll0_sysclk5",
107 static struct clk pll0_sysclk6 = {
108 .name = "pll0_sysclk6",
114 static struct clk pll0_sysclk7 = {
115 .name = "pll0_sysclk7",
121 static struct pll_data pll1_data = {
123 .phys_base = DA850_PLL1_BASE,
124 .flags = PLL_HAS_POSTDIV,
127 static struct clk pll1_clk = {
130 .pll_data = &pll1_data,
134 static struct clk pll1_aux_clk = {
135 .name = "pll1_aux_clk",
137 .flags = CLK_PLL | PRE_PLL,
140 static struct clk pll1_sysclk2 = {
141 .name = "pll1_sysclk2",
147 static struct clk pll1_sysclk3 = {
148 .name = "pll1_sysclk3",
154 static struct clk pll1_sysclk4 = {
155 .name = "pll1_sysclk4",
161 static struct clk pll1_sysclk5 = {
162 .name = "pll1_sysclk5",
168 static struct clk pll1_sysclk6 = {
169 .name = "pll0_sysclk6",
175 static struct clk pll1_sysclk7 = {
176 .name = "pll1_sysclk7",
182 static struct clk i2c0_clk = {
184 .parent = &pll0_aux_clk,
187 static struct clk timerp64_0_clk = {
189 .parent = &pll0_aux_clk,
192 static struct clk timerp64_1_clk = {
194 .parent = &pll0_aux_clk,
197 static struct clk arm_rom_clk = {
199 .parent = &pll0_sysclk2,
200 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
201 .flags = ALWAYS_ENABLED,
204 static struct clk tpcc0_clk = {
206 .parent = &pll0_sysclk2,
207 .lpsc = DA8XX_LPSC0_TPCC,
208 .flags = ALWAYS_ENABLED | CLK_PSC,
211 static struct clk tptc0_clk = {
213 .parent = &pll0_sysclk2,
214 .lpsc = DA8XX_LPSC0_TPTC0,
215 .flags = ALWAYS_ENABLED,
218 static struct clk tptc1_clk = {
220 .parent = &pll0_sysclk2,
221 .lpsc = DA8XX_LPSC0_TPTC1,
222 .flags = ALWAYS_ENABLED,
225 static struct clk tpcc1_clk = {
227 .parent = &pll0_sysclk2,
228 .lpsc = DA850_LPSC1_TPCC1,
230 .flags = CLK_PSC | ALWAYS_ENABLED,
233 static struct clk tptc2_clk = {
235 .parent = &pll0_sysclk2,
236 .lpsc = DA850_LPSC1_TPTC2,
238 .flags = ALWAYS_ENABLED,
241 static struct clk uart0_clk = {
243 .parent = &pll0_sysclk2,
244 .lpsc = DA8XX_LPSC0_UART0,
247 static struct clk uart1_clk = {
249 .parent = &pll0_sysclk2,
250 .lpsc = DA8XX_LPSC1_UART1,
252 .flags = DA850_CLK_ASYNC3,
255 static struct clk uart2_clk = {
257 .parent = &pll0_sysclk2,
258 .lpsc = DA8XX_LPSC1_UART2,
260 .flags = DA850_CLK_ASYNC3,
263 static struct clk aintc_clk = {
265 .parent = &pll0_sysclk4,
266 .lpsc = DA8XX_LPSC0_AINTC,
267 .flags = ALWAYS_ENABLED,
270 static struct clk gpio_clk = {
272 .parent = &pll0_sysclk4,
273 .lpsc = DA8XX_LPSC1_GPIO,
277 static struct clk i2c1_clk = {
279 .parent = &pll0_sysclk4,
280 .lpsc = DA8XX_LPSC1_I2C,
284 static struct clk emif3_clk = {
286 .parent = &pll0_sysclk5,
287 .lpsc = DA8XX_LPSC1_EMIF3C,
289 .flags = ALWAYS_ENABLED,
292 static struct clk arm_clk = {
294 .parent = &pll0_sysclk6,
295 .lpsc = DA8XX_LPSC0_ARM,
296 .flags = ALWAYS_ENABLED,
297 .set_rate = da850_set_armrate,
298 .round_rate = da850_round_armrate,
301 static struct clk rmii_clk = {
303 .parent = &pll0_sysclk7,
306 static struct clk emac_clk = {
308 .parent = &pll0_sysclk4,
309 .lpsc = DA8XX_LPSC1_CPGMAC,
313 static struct clk mcasp_clk = {
315 .parent = &pll0_sysclk2,
316 .lpsc = DA8XX_LPSC1_McASP0,
318 .flags = DA850_CLK_ASYNC3,
321 static struct clk lcdc_clk = {
323 .parent = &pll0_sysclk2,
324 .lpsc = DA8XX_LPSC1_LCDC,
328 static struct clk mmcsd0_clk = {
330 .parent = &pll0_sysclk2,
331 .lpsc = DA8XX_LPSC0_MMC_SD,
334 static struct clk mmcsd1_clk = {
336 .parent = &pll0_sysclk2,
337 .lpsc = DA850_LPSC1_MMC_SD1,
341 static struct clk aemif_clk = {
343 .parent = &pll0_sysclk3,
344 .lpsc = DA8XX_LPSC0_EMIF25,
345 .flags = ALWAYS_ENABLED,
348 static struct clk usb11_clk = {
350 .parent = &pll0_sysclk4,
351 .lpsc = DA8XX_LPSC1_USB11,
355 static struct clk usb20_clk = {
357 .parent = &pll0_sysclk2,
358 .lpsc = DA8XX_LPSC1_USB20,
362 static struct clk_lookup da850_clks[] = {
363 CLK(NULL, "ref", &ref_clk),
364 CLK(NULL, "pll0", &pll0_clk),
365 CLK(NULL, "pll0_aux", &pll0_aux_clk),
366 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
367 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
368 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
369 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
370 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
371 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
372 CLK(NULL, "pll1", &pll1_clk),
373 CLK(NULL, "pll1_aux", &pll1_aux_clk),
374 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
375 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
376 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
377 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
378 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
379 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
380 CLK("i2c_davinci.1", NULL, &i2c0_clk),
381 CLK(NULL, "timer0", &timerp64_0_clk),
382 CLK("watchdog", NULL, &timerp64_1_clk),
383 CLK(NULL, "arm_rom", &arm_rom_clk),
384 CLK(NULL, "tpcc0", &tpcc0_clk),
385 CLK(NULL, "tptc0", &tptc0_clk),
386 CLK(NULL, "tptc1", &tptc1_clk),
387 CLK(NULL, "tpcc1", &tpcc1_clk),
388 CLK(NULL, "tptc2", &tptc2_clk),
389 CLK(NULL, "uart0", &uart0_clk),
390 CLK(NULL, "uart1", &uart1_clk),
391 CLK(NULL, "uart2", &uart2_clk),
392 CLK(NULL, "aintc", &aintc_clk),
393 CLK(NULL, "gpio", &gpio_clk),
394 CLK("i2c_davinci.2", NULL, &i2c1_clk),
395 CLK(NULL, "emif3", &emif3_clk),
396 CLK(NULL, "arm", &arm_clk),
397 CLK(NULL, "rmii", &rmii_clk),
398 CLK("davinci_emac.1", NULL, &emac_clk),
399 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
400 CLK("da8xx_lcdc.0", NULL, &lcdc_clk),
401 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
402 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
403 CLK(NULL, "aemif", &aemif_clk),
404 CLK(NULL, "usb11", &usb11_clk),
405 CLK(NULL, "usb20", &usb20_clk),
406 CLK(NULL, NULL, NULL),
410 * Device specific mux setup
412 * soc description mux mode mode mux dbg
413 * reg offset mask mode
415 static const struct mux_config da850_pins[] = {
416 #ifdef CONFIG_DAVINCI_MUX
418 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
419 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
420 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
421 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
423 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
424 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
426 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
427 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
429 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
430 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
432 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
433 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
435 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
436 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
437 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
438 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
439 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
440 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
441 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
442 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
443 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
444 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
445 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
446 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
447 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
448 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
449 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
450 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
451 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
452 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
453 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
454 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
455 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
456 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
457 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
458 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
459 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
461 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
462 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
463 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
464 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
465 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
466 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
467 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
468 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
469 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
470 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
471 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
472 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
473 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
474 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
475 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
476 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
477 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
478 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
479 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
480 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
481 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
482 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
483 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
485 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
486 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
487 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
488 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
489 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
490 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
491 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
492 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
493 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
494 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
495 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
496 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
497 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
498 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
499 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
500 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
501 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
502 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
503 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
504 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
505 /* MMC/SD0 function */
506 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
507 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
508 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
509 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
510 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
511 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
512 /* EMIF2.5/EMIFA function */
513 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
514 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
515 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
516 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
517 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
518 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
519 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
520 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
521 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
522 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
523 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
524 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
525 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
526 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
527 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
528 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
529 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
530 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
531 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
532 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
533 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
534 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
535 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
536 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
537 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
538 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
539 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
540 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
541 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
542 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
543 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
544 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
545 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
546 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
547 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
548 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
549 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
550 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
551 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
552 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
553 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
554 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
555 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
556 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
557 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
558 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
559 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
560 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
562 MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false)
563 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
564 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
565 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
566 MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false)
567 MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false)
568 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
569 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
570 MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false)
571 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
575 const short da850_uart0_pins[] __initdata = {
576 DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
580 const short da850_uart1_pins[] __initdata = {
581 DA850_UART1_RXD, DA850_UART1_TXD,
585 const short da850_uart2_pins[] __initdata = {
586 DA850_UART2_RXD, DA850_UART2_TXD,
590 const short da850_i2c0_pins[] __initdata = {
591 DA850_I2C0_SDA, DA850_I2C0_SCL,
595 const short da850_i2c1_pins[] __initdata = {
596 DA850_I2C1_SCL, DA850_I2C1_SDA,
600 const short da850_mcasp_pins[] __initdata = {
601 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
602 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
603 DA850_AXR_11, DA850_AXR_12,
607 const short da850_lcdcntl_pins[] __initdata = {
608 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
609 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
610 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
611 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
612 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
616 const short da850_mmcsd0_pins[] __initdata = {
617 DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
618 DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
619 DA850_GPIO4_0, DA850_GPIO4_1,
623 const short da850_emif25_pins[] __initdata = {
624 DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
625 DA850_NEMA_CS_3, DA850_NEMA_CS_4, DA850_NEMA_WE, DA850_NEMA_OE,
626 DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3,
627 DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7,
628 DA850_EMA_D_8, DA850_EMA_D_9, DA850_EMA_D_10, DA850_EMA_D_11,
629 DA850_EMA_D_12, DA850_EMA_D_13, DA850_EMA_D_14, DA850_EMA_D_15,
630 DA850_EMA_A_0, DA850_EMA_A_1, DA850_EMA_A_2, DA850_EMA_A_3,
631 DA850_EMA_A_4, DA850_EMA_A_5, DA850_EMA_A_6, DA850_EMA_A_7,
632 DA850_EMA_A_8, DA850_EMA_A_9, DA850_EMA_A_10, DA850_EMA_A_11,
633 DA850_EMA_A_12, DA850_EMA_A_13, DA850_EMA_A_14, DA850_EMA_A_15,
634 DA850_EMA_A_16, DA850_EMA_A_17, DA850_EMA_A_18, DA850_EMA_A_19,
635 DA850_EMA_A_20, DA850_EMA_A_21, DA850_EMA_A_22, DA850_EMA_A_23,
639 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
640 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
641 [IRQ_DA8XX_COMMTX] = 7,
642 [IRQ_DA8XX_COMMRX] = 7,
643 [IRQ_DA8XX_NINT] = 7,
644 [IRQ_DA8XX_EVTOUT0] = 7,
645 [IRQ_DA8XX_EVTOUT1] = 7,
646 [IRQ_DA8XX_EVTOUT2] = 7,
647 [IRQ_DA8XX_EVTOUT3] = 7,
648 [IRQ_DA8XX_EVTOUT4] = 7,
649 [IRQ_DA8XX_EVTOUT5] = 7,
650 [IRQ_DA8XX_EVTOUT6] = 7,
651 [IRQ_DA8XX_EVTOUT7] = 7,
652 [IRQ_DA8XX_CCINT0] = 7,
653 [IRQ_DA8XX_CCERRINT] = 7,
654 [IRQ_DA8XX_TCERRINT0] = 7,
655 [IRQ_DA8XX_AEMIFINT] = 7,
656 [IRQ_DA8XX_I2CINT0] = 7,
657 [IRQ_DA8XX_MMCSDINT0] = 7,
658 [IRQ_DA8XX_MMCSDINT1] = 7,
659 [IRQ_DA8XX_ALLINT0] = 7,
661 [IRQ_DA8XX_SPINT0] = 7,
662 [IRQ_DA8XX_TINT12_0] = 7,
663 [IRQ_DA8XX_TINT34_0] = 7,
664 [IRQ_DA8XX_TINT12_1] = 7,
665 [IRQ_DA8XX_TINT34_1] = 7,
666 [IRQ_DA8XX_UARTINT0] = 7,
667 [IRQ_DA8XX_KEYMGRINT] = 7,
668 [IRQ_DA850_MPUADDRERR0] = 7,
669 [IRQ_DA8XX_CHIPINT0] = 7,
670 [IRQ_DA8XX_CHIPINT1] = 7,
671 [IRQ_DA8XX_CHIPINT2] = 7,
672 [IRQ_DA8XX_CHIPINT3] = 7,
673 [IRQ_DA8XX_TCERRINT1] = 7,
674 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
675 [IRQ_DA8XX_C0_RX_PULSE] = 7,
676 [IRQ_DA8XX_C0_TX_PULSE] = 7,
677 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
678 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
679 [IRQ_DA8XX_C1_RX_PULSE] = 7,
680 [IRQ_DA8XX_C1_TX_PULSE] = 7,
681 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
682 [IRQ_DA8XX_MEMERR] = 7,
683 [IRQ_DA8XX_GPIO0] = 7,
684 [IRQ_DA8XX_GPIO1] = 7,
685 [IRQ_DA8XX_GPIO2] = 7,
686 [IRQ_DA8XX_GPIO3] = 7,
687 [IRQ_DA8XX_GPIO4] = 7,
688 [IRQ_DA8XX_GPIO5] = 7,
689 [IRQ_DA8XX_GPIO6] = 7,
690 [IRQ_DA8XX_GPIO7] = 7,
691 [IRQ_DA8XX_GPIO8] = 7,
692 [IRQ_DA8XX_I2CINT1] = 7,
693 [IRQ_DA8XX_LCDINT] = 7,
694 [IRQ_DA8XX_UARTINT1] = 7,
695 [IRQ_DA8XX_MCASPINT] = 7,
696 [IRQ_DA8XX_ALLINT1] = 7,
697 [IRQ_DA8XX_SPINT1] = 7,
698 [IRQ_DA8XX_UHPI_INT1] = 7,
699 [IRQ_DA8XX_USB_INT] = 7,
700 [IRQ_DA8XX_IRQN] = 7,
701 [IRQ_DA8XX_RWAKEUP] = 7,
702 [IRQ_DA8XX_UARTINT2] = 7,
703 [IRQ_DA8XX_DFTSSINT] = 7,
704 [IRQ_DA8XX_EHRPWM0] = 7,
705 [IRQ_DA8XX_EHRPWM0TZ] = 7,
706 [IRQ_DA8XX_EHRPWM1] = 7,
707 [IRQ_DA8XX_EHRPWM1TZ] = 7,
708 [IRQ_DA850_SATAINT] = 7,
709 [IRQ_DA850_TINTALL_2] = 7,
710 [IRQ_DA8XX_ECAP0] = 7,
711 [IRQ_DA8XX_ECAP1] = 7,
712 [IRQ_DA8XX_ECAP2] = 7,
713 [IRQ_DA850_MMCSDINT0_1] = 7,
714 [IRQ_DA850_MMCSDINT1_1] = 7,
715 [IRQ_DA850_T12CMPINT0_2] = 7,
716 [IRQ_DA850_T12CMPINT1_2] = 7,
717 [IRQ_DA850_T12CMPINT2_2] = 7,
718 [IRQ_DA850_T12CMPINT3_2] = 7,
719 [IRQ_DA850_T12CMPINT4_2] = 7,
720 [IRQ_DA850_T12CMPINT5_2] = 7,
721 [IRQ_DA850_T12CMPINT6_2] = 7,
722 [IRQ_DA850_T12CMPINT7_2] = 7,
723 [IRQ_DA850_T12CMPINT0_3] = 7,
724 [IRQ_DA850_T12CMPINT1_3] = 7,
725 [IRQ_DA850_T12CMPINT2_3] = 7,
726 [IRQ_DA850_T12CMPINT3_3] = 7,
727 [IRQ_DA850_T12CMPINT4_3] = 7,
728 [IRQ_DA850_T12CMPINT5_3] = 7,
729 [IRQ_DA850_T12CMPINT6_3] = 7,
730 [IRQ_DA850_T12CMPINT7_3] = 7,
731 [IRQ_DA850_RPIINT] = 7,
732 [IRQ_DA850_VPIFINT] = 7,
733 [IRQ_DA850_CCINT1] = 7,
734 [IRQ_DA850_CCERRINT1] = 7,
735 [IRQ_DA850_TCERRINT2] = 7,
736 [IRQ_DA850_TINTALL_3] = 7,
737 [IRQ_DA850_MCBSP0RINT] = 7,
738 [IRQ_DA850_MCBSP0XINT] = 7,
739 [IRQ_DA850_MCBSP1RINT] = 7,
740 [IRQ_DA850_MCBSP1XINT] = 7,
741 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
744 static struct map_desc da850_io_desc[] = {
747 .pfn = __phys_to_pfn(IO_PHYS),
752 .virtual = DA8XX_CP_INTC_VIRT,
753 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
754 .length = DA8XX_CP_INTC_SIZE,
758 .virtual = SRAM_VIRT,
759 .pfn = __phys_to_pfn(DA8XX_ARM_RAM_BASE),
765 static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
767 /* Contents of JTAG ID register used to identify exact cpu type */
768 static struct davinci_id da850_ids[] = {
772 .manufacturer = 0x017, /* 0x02f >> 1 */
773 .cpu_id = DAVINCI_CPU_ID_DA850,
774 .name = "da850/omap-l138",
779 .manufacturer = 0x017, /* 0x02f >> 1 */
780 .cpu_id = DAVINCI_CPU_ID_DA850,
781 .name = "da850/omap-l138/am18x",
785 static struct davinci_timer_instance da850_timer_instance[4] = {
787 .base = DA8XX_TIMER64P0_BASE,
788 .bottom_irq = IRQ_DA8XX_TINT12_0,
789 .top_irq = IRQ_DA8XX_TINT34_0,
792 .base = DA8XX_TIMER64P1_BASE,
793 .bottom_irq = IRQ_DA8XX_TINT12_1,
794 .top_irq = IRQ_DA8XX_TINT34_1,
797 .base = DA850_TIMER64P2_BASE,
798 .bottom_irq = IRQ_DA850_TINT12_2,
799 .top_irq = IRQ_DA850_TINT34_2,
802 .base = DA850_TIMER64P3_BASE,
803 .bottom_irq = IRQ_DA850_TINT12_3,
804 .top_irq = IRQ_DA850_TINT34_3,
809 * T0_BOT: Timer 0, bottom : Used for clock_event
810 * T0_TOP: Timer 0, top : Used for clocksource
811 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
813 static struct davinci_timer_info da850_timer_info = {
814 .timers = da850_timer_instance,
815 .clockevent_id = T0_BOT,
816 .clocksource_id = T0_TOP,
819 static void da850_set_async3_src(int pllnum)
821 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
822 struct clk_lookup *c;
826 for (c = da850_clks; c->clk; c++) {
828 if (clk->flags & DA850_CLK_ASYNC3) {
829 ret = clk_set_parent(clk, newparent);
830 WARN(ret, "DA850: unable to re-parent clock %s",
835 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
837 v |= CFGCHIP3_ASYNC3_CLKSRC;
839 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
840 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
843 #ifdef CONFIG_CPU_FREQ
846 * According to the TRM, minimum PLLM results in maximum power savings.
847 * The OPP definitions below should keep the PLLM as low as possible.
849 * The output of the PLLM must be between 300 to 600 MHz.
852 unsigned int freq; /* in KHz */
855 unsigned int postdiv;
856 unsigned int cvdd_min; /* in uV */
857 unsigned int cvdd_max; /* in uV */
860 static const struct da850_opp da850_opp_456 = {
869 static const struct da850_opp da850_opp_408 = {
878 static const struct da850_opp da850_opp_372 = {
887 static const struct da850_opp da850_opp_300 = {
896 static const struct da850_opp da850_opp_200 = {
905 static const struct da850_opp da850_opp_96 = {
916 .index = (unsigned int) &da850_opp_##freq, \
917 .frequency = freq * 1000, \
920 static struct cpufreq_frequency_table da850_freq_table[] = {
929 .frequency = CPUFREQ_TABLE_END,
933 #ifdef CONFIG_REGULATOR
934 static int da850_set_voltage(unsigned int index);
935 static int da850_regulator_init(void);
938 static struct davinci_cpufreq_config cpufreq_info = {
939 .freq_table = da850_freq_table,
940 #ifdef CONFIG_REGULATOR
941 .init = da850_regulator_init,
942 .set_voltage = da850_set_voltage,
946 #ifdef CONFIG_REGULATOR
947 static struct regulator *cvdd;
949 static int da850_set_voltage(unsigned int index)
951 struct da850_opp *opp;
956 opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
958 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
961 static int da850_regulator_init(void)
963 cvdd = regulator_get(NULL, "cvdd");
964 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
965 " voltage scaling unsupported\n")) {
966 return PTR_ERR(cvdd);
973 static struct platform_device da850_cpufreq_device = {
974 .name = "cpufreq-davinci",
976 .platform_data = &cpufreq_info,
981 unsigned int da850_max_speed = 300000;
983 int __init da850_register_cpufreq(char *async_clk)
987 /* cpufreq driver can help keep an "async" clock constant */
989 clk_add_alias("async", da850_cpufreq_device.name,
991 for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
992 if (da850_freq_table[i].frequency <= da850_max_speed) {
993 cpufreq_info.freq_table = &da850_freq_table[i];
998 return platform_device_register(&da850_cpufreq_device);
1001 static int da850_round_armrate(struct clk *clk, unsigned long rate)
1003 int i, ret = 0, diff;
1004 unsigned int best = (unsigned int) -1;
1005 struct cpufreq_frequency_table *table = cpufreq_info.freq_table;
1007 rate /= 1000; /* convert to kHz */
1009 for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
1010 diff = table[i].frequency - rate;
1016 ret = table[i].frequency;
1023 static int da850_set_armrate(struct clk *clk, unsigned long index)
1025 struct clk *pllclk = &pll0_clk;
1027 return clk_set_rate(pllclk, index);
1030 static int da850_set_pll0rate(struct clk *clk, unsigned long index)
1032 unsigned int prediv, mult, postdiv;
1033 struct da850_opp *opp;
1034 struct pll_data *pll = clk->pll_data;
1037 opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
1038 prediv = opp->prediv;
1040 postdiv = opp->postdiv;
1042 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
1049 int __init da850_register_cpufreq(char *async_clk)
1054 static int da850_set_armrate(struct clk *clk, unsigned long rate)
1059 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
1064 static int da850_round_armrate(struct clk *clk, unsigned long rate)
1070 int da850_register_pm(struct platform_device *pdev)
1073 struct davinci_pm_config *pdata = pdev->dev.platform_data;
1075 ret = davinci_cfg_reg(DA850_RTC_ALARM);
1079 pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
1080 pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
1081 pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
1083 pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
1084 if (!pdata->cpupll_reg_base)
1087 pdata->ddrpll_reg_base = ioremap(DA8XX_PLL1_BASE, SZ_4K);
1088 if (!pdata->ddrpll_reg_base) {
1093 pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
1094 if (!pdata->ddrpsc_reg_base) {
1099 return platform_device_register(pdev);
1102 iounmap(pdata->ddrpll_reg_base);
1104 iounmap(pdata->cpupll_reg_base);
1108 static struct davinci_soc_info davinci_soc_info_da850 = {
1109 .io_desc = da850_io_desc,
1110 .io_desc_num = ARRAY_SIZE(da850_io_desc),
1111 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
1113 .ids_num = ARRAY_SIZE(da850_ids),
1114 .cpu_clks = da850_clks,
1115 .psc_bases = da850_psc_bases,
1116 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
1117 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
1118 .pinmux_pins = da850_pins,
1119 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
1120 .intc_base = DA8XX_CP_INTC_BASE,
1121 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
1122 .intc_irq_prios = da850_default_priorities,
1123 .intc_irq_num = DA850_N_CP_INTC_IRQ,
1124 .timer_info = &da850_timer_info,
1125 .gpio_type = GPIO_TYPE_DAVINCI,
1126 .gpio_base = DA8XX_GPIO_BASE,
1128 .gpio_irq = IRQ_DA8XX_GPIO0,
1129 .serial_dev = &da8xx_serial_device,
1130 .emac_pdata = &da8xx_emac_pdata,
1131 .sram_dma = DA8XX_ARM_RAM_BASE,
1133 .reset_device = &da8xx_wdt_device,
1136 void __init da850_init(void)
1140 davinci_common_init(&davinci_soc_info_da850);
1142 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1143 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1146 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
1147 if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
1151 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
1152 * This helps keeping the peripherals on this domain insulated
1153 * from CPU frequency changes caused by DVFS. The firmware sets
1154 * both PLL0 and PLL1 to the same frequency so, there should not
1155 * be any noticible change even in non-DVFS use cases.
1157 da850_set_async3_src(1);
1159 /* Unlock writing to PLL0 registers */
1160 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1161 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1162 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1164 /* Unlock writing to PLL1 registers */
1165 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1166 v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
1167 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));