2 * TI DaVinci DM365 EVM board support
4 * Copyright (C) 2009 Texas Instruments Incorporated
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/err.h>
18 #include <linux/i2c.h>
20 #include <linux/clk.h>
21 #include <linux/i2c/at24.h>
22 #include <linux/leds.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/partitions.h>
25 #include <linux/slab.h>
26 #include <linux/mtd/nand.h>
27 #include <linux/input.h>
28 #include <linux/spi/spi.h>
29 #include <linux/spi/eeprom.h>
31 #include <asm/mach-types.h>
32 #include <asm/mach/arch.h>
35 #include <mach/dm365.h>
36 #include <mach/common.h>
38 #include <mach/serial.h>
40 #include <mach/nand.h>
41 #include <mach/keyscan.h>
43 #include <media/tvp514x.h>
45 static inline int have_imager(void)
47 /* REVISIT when it's supported, trigger via Kconfig */
51 static inline int have_tvp7002(void)
53 /* REVISIT when it's supported, trigger via Kconfig */
57 #define DM365_EVM_PHY_ID "0:01"
59 * A MAX-II CPLD is used for various board control functions.
61 #define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3))
63 #define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */
64 #define CPLD_TEST CPLD_OFFSET(0,1)
65 #define CPLD_LEDS CPLD_OFFSET(0,2)
66 #define CPLD_MUX CPLD_OFFSET(0,3)
67 #define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */
68 #define CPLD_POWER CPLD_OFFSET(1,1)
69 #define CPLD_VIDEO CPLD_OFFSET(1,2)
70 #define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */
72 #define CPLD_DILC_OUT CPLD_OFFSET(2,0)
73 #define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */
75 #define CPLD_IMG_DIR0 CPLD_OFFSET(2,2)
76 #define CPLD_IMG_MUX0 CPLD_OFFSET(2,3)
77 #define CPLD_IMG_MUX1 CPLD_OFFSET(3,0)
78 #define CPLD_IMG_DIR1 CPLD_OFFSET(3,1)
79 #define CPLD_IMG_MUX2 CPLD_OFFSET(3,2)
80 #define CPLD_IMG_MUX3 CPLD_OFFSET(3,3)
81 #define CPLD_IMG_DIR2 CPLD_OFFSET(4,0)
82 #define CPLD_IMG_MUX4 CPLD_OFFSET(4,1)
83 #define CPLD_IMG_MUX5 CPLD_OFFSET(4,2)
85 #define CPLD_RESETS CPLD_OFFSET(4,3)
87 #define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0)
88 #define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1)
89 #define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2)
90 #define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3)
91 #define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0)
92 #define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1)
94 static void __iomem *cpld;
97 /* NOTE: this is geared for the standard config, with a socketed
98 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
99 * swap chips with a different block size, partitioning will
100 * need to be changed. This NAND chip MT29F16G08FAA is the default
101 * NAND shipped with the Spectrum Digital DM365 EVM
103 #define NAND_BLOCK_SIZE SZ_128K
105 static struct mtd_partition davinci_nand_partitions[] = {
107 /* UBL (a few copies) plus U-Boot */
108 .name = "bootloader",
110 .size = 28 * NAND_BLOCK_SIZE,
111 .mask_flags = MTD_WRITEABLE, /* force read-only */
113 /* U-Boot environment */
115 .offset = MTDPART_OFS_APPEND,
116 .size = 2 * NAND_BLOCK_SIZE,
120 .offset = MTDPART_OFS_APPEND,
124 .name = "filesystem1",
125 .offset = MTDPART_OFS_APPEND,
129 .name = "filesystem2",
130 .offset = MTDPART_OFS_APPEND,
131 .size = MTDPART_SIZ_FULL,
134 /* two blocks with bad block table (and mirror) at the end */
137 static struct davinci_nand_pdata davinci_nand_data = {
138 .mask_chipsel = BIT(14),
139 .parts = davinci_nand_partitions,
140 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
141 .ecc_mode = NAND_ECC_HW,
142 .options = NAND_USE_FLASH_BBT,
146 static struct resource davinci_nand_resources[] = {
148 .start = DM365_ASYNC_EMIF_DATA_CE0_BASE,
149 .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
150 .flags = IORESOURCE_MEM,
152 .start = DM365_ASYNC_EMIF_CONTROL_BASE,
153 .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
154 .flags = IORESOURCE_MEM,
158 static struct platform_device davinci_nand_device = {
159 .name = "davinci_nand",
161 .num_resources = ARRAY_SIZE(davinci_nand_resources),
162 .resource = davinci_nand_resources,
164 .platform_data = &davinci_nand_data,
168 static struct at24_platform_data eeprom_info = {
169 .byte_len = (256*1024) / 8,
171 .flags = AT24_FLAG_ADDR16,
172 .setup = davinci_get_mac_addr,
173 .context = (void *)0x7f00,
176 static struct snd_platform_data dm365_evm_snd_data = {
177 .asp_chan_q = EVENTQ_3,
180 static struct i2c_board_info i2c_info[] = {
182 I2C_BOARD_INFO("24c256", 0x50),
183 .platform_data = &eeprom_info,
186 I2C_BOARD_INFO("tlv320aic3x", 0x18),
190 static struct davinci_i2c_platform_data i2c_pdata = {
191 .bus_freq = 400 /* kHz */,
192 .bus_delay = 0 /* usec */,
195 static int dm365evm_keyscan_enable(struct device *dev)
197 return davinci_cfg_reg(DM365_KEYSCAN);
200 static unsigned short dm365evm_keymap[] = {
220 static struct davinci_ks_platform_data dm365evm_ks_data = {
221 .device_enable = dm365evm_keyscan_enable,
222 .keymap = dm365evm_keymap,
223 .keymapsize = ARRAY_SIZE(dm365evm_keymap),
225 /* Scan period = strobe + interval */
228 .matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4,
231 static int cpld_mmc_get_cd(int module)
236 /* low == card present */
237 return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
240 static int cpld_mmc_get_ro(int module)
245 /* high == card's write protect switch active */
246 return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
249 static struct davinci_mmc_config dm365evm_mmc_config = {
250 .get_cd = cpld_mmc_get_cd,
251 .get_ro = cpld_mmc_get_ro,
253 .max_freq = 50000000,
254 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
255 .version = MMC_CTLR_VERSION_2,
258 static void dm365evm_emac_configure(void)
261 * EMAC pins are multiplexed with GPIO and UART
262 * Further details are available at the DM365 ARM
263 * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
265 davinci_cfg_reg(DM365_EMAC_TX_EN);
266 davinci_cfg_reg(DM365_EMAC_TX_CLK);
267 davinci_cfg_reg(DM365_EMAC_COL);
268 davinci_cfg_reg(DM365_EMAC_TXD3);
269 davinci_cfg_reg(DM365_EMAC_TXD2);
270 davinci_cfg_reg(DM365_EMAC_TXD1);
271 davinci_cfg_reg(DM365_EMAC_TXD0);
272 davinci_cfg_reg(DM365_EMAC_RXD3);
273 davinci_cfg_reg(DM365_EMAC_RXD2);
274 davinci_cfg_reg(DM365_EMAC_RXD1);
275 davinci_cfg_reg(DM365_EMAC_RXD0);
276 davinci_cfg_reg(DM365_EMAC_RX_CLK);
277 davinci_cfg_reg(DM365_EMAC_RX_DV);
278 davinci_cfg_reg(DM365_EMAC_RX_ER);
279 davinci_cfg_reg(DM365_EMAC_CRS);
280 davinci_cfg_reg(DM365_EMAC_MDIO);
281 davinci_cfg_reg(DM365_EMAC_MDCLK);
284 * EMAC interrupts are multiplexed with GPIO interrupts
285 * Details are available at the DM365 ARM
286 * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
288 davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
289 davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
290 davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
291 davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
294 static void dm365evm_mmc_configure(void)
297 * MMC/SD pins are multiplexed with GPIO and EMIF
298 * Further details are available at the DM365 ARM
299 * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
301 davinci_cfg_reg(DM365_SD1_CLK);
302 davinci_cfg_reg(DM365_SD1_CMD);
303 davinci_cfg_reg(DM365_SD1_DATA3);
304 davinci_cfg_reg(DM365_SD1_DATA2);
305 davinci_cfg_reg(DM365_SD1_DATA1);
306 davinci_cfg_reg(DM365_SD1_DATA0);
309 static struct tvp514x_platform_data tvp5146_pdata = {
315 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
316 /* Inputs available at the TVP5146 */
317 static struct v4l2_input tvp5146_inputs[] = {
321 .type = V4L2_INPUT_TYPE_CAMERA,
322 .std = TVP514X_STD_ALL,
327 .type = V4L2_INPUT_TYPE_CAMERA,
328 .std = TVP514X_STD_ALL,
333 * this is the route info for connecting each input to decoder
334 * ouput that goes to vpfe. There is a one to one correspondence
335 * with tvp5146_inputs
337 static struct vpfe_route tvp5146_routes[] = {
339 .input = INPUT_CVBS_VI2B,
340 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
343 .input = INPUT_SVIDEO_VI2C_VI1C,
344 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
348 static struct vpfe_subdev_info vpfe_sub_devs[] = {
352 .num_inputs = ARRAY_SIZE(tvp5146_inputs),
353 .inputs = tvp5146_inputs,
354 .routes = tvp5146_routes,
357 .if_type = VPFE_BT656,
358 .hdpol = VPFE_PINPOL_POSITIVE,
359 .vdpol = VPFE_PINPOL_POSITIVE,
362 I2C_BOARD_INFO("tvp5146", 0x5d),
363 .platform_data = &tvp5146_pdata,
368 static struct vpfe_config vpfe_cfg = {
369 .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
370 .sub_devs = vpfe_sub_devs,
372 .card_name = "DM365 EVM",
376 static void __init evm_init_i2c(void)
378 davinci_init_i2c(&i2c_pdata);
379 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
382 static struct platform_device *dm365_evm_nand_devices[] __initdata = {
383 &davinci_nand_device,
386 static inline int have_leds(void)
388 #ifdef CONFIG_LEDS_CLASS
396 struct led_classdev cdev;
400 static const struct {
404 { "dm365evm::ds2", },
405 { "dm365evm::ds3", },
406 { "dm365evm::ds4", },
407 { "dm365evm::ds5", },
408 { "dm365evm::ds6", "nand-disk", },
409 { "dm365evm::ds7", "mmc1", },
410 { "dm365evm::ds8", "mmc0", },
411 { "dm365evm::ds9", "heartbeat", },
414 static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
416 struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
417 u8 reg = __raw_readb(cpld + CPLD_LEDS);
423 __raw_writeb(reg, cpld + CPLD_LEDS);
426 static enum led_brightness cpld_led_get(struct led_classdev *cdev)
428 struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
429 u8 reg = __raw_readb(cpld + CPLD_LEDS);
431 return (reg & led->mask) ? LED_OFF : LED_FULL;
434 static int __init cpld_leds_init(void)
438 if (!have_leds() || !cpld)
442 __raw_writeb(0xff, cpld + CPLD_LEDS);
443 for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
444 struct cpld_led *led;
446 led = kzalloc(sizeof(*led), GFP_KERNEL);
450 led->cdev.name = cpld_leds[i].name;
451 led->cdev.brightness_set = cpld_led_set;
452 led->cdev.brightness_get = cpld_led_get;
453 led->cdev.default_trigger = cpld_leds[i].trigger;
456 if (led_classdev_register(NULL, &led->cdev) < 0) {
464 /* run after subsys_initcall() for LEDs */
465 fs_initcall(cpld_leds_init);
468 static void __init evm_init_cpld(void)
472 struct clk *aemif_clk;
474 /* Make sure we can configure the CPLD through CS1. Then
475 * leave it on for later access to MMC and LED registers.
477 aemif_clk = clk_get(NULL, "aemif");
478 if (IS_ERR(aemif_clk))
480 clk_enable(aemif_clk);
482 if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
485 cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
487 release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
490 pr_err("ERROR: can't map CPLD\n");
491 clk_disable(aemif_clk);
495 /* External muxing for some signals */
498 /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
499 * NOTE: SW4 bus width setting must match!
501 if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
502 /* external keypad mux */
505 platform_add_devices(dm365_evm_nand_devices,
506 ARRAY_SIZE(dm365_evm_nand_devices));
508 /* no OneNAND support yet */
511 /* Leave external chips in reset when unused. */
512 resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
514 /* Static video input config with SN74CBT16214 1-of-3 mux:
515 * - port b1 == tvp7002 (mux lowbits == 1 or 6)
516 * - port b2 == imager (mux lowbits == 2 or 7)
517 * - port b3 == tvp5146 (mux lowbits == 5)
519 * Runtime switching could work too, with limitations.
525 /* externally mux MMC1/ENET/AIC33 to imager */
526 mux |= BIT(6) | BIT(5) | BIT(3);
528 struct davinci_soc_info *soc_info = &davinci_soc_info;
530 /* we can use MMC1 ... */
531 dm365evm_mmc_configure();
532 davinci_setup_mmc(1, &dm365evm_mmc_config);
534 /* ... and ENET ... */
535 dm365evm_emac_configure();
536 soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID;
542 if (have_tvp7002()) {
545 label = "tvp7002 HD";
547 /* default to tvp5146 */
550 label = "tvp5146 SD";
553 __raw_writeb(mux, cpld + CPLD_MUX);
554 __raw_writeb(resets, cpld + CPLD_RESETS);
555 pr_info("EVM: %s video input\n", label);
557 /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
560 static struct davinci_uart_config uart_config __initdata = {
561 .enabled_uarts = (1 << 0),
564 static void __init dm365_evm_map_io(void)
566 /* setup input configuration for VPFE input devices */
567 dm365_set_vpfe_config(&vpfe_cfg);
571 static struct spi_eeprom at25640 = {
572 .byte_len = SZ_64K / 8,
578 static struct spi_board_info dm365_evm_spi_info[] __initconst = {
581 .platform_data = &at25640,
582 .max_speed_hz = 10 * 1000 * 1000,
589 static __init void dm365_evm_init(void)
592 davinci_serial_init(&uart_config);
594 dm365evm_emac_configure();
595 dm365evm_mmc_configure();
597 davinci_setup_mmc(0, &dm365evm_mmc_config);
599 /* maybe setup mmc1/etc ... _after_ mmc0 */
602 #ifdef CONFIG_SND_DM365_AIC3X_CODEC
603 dm365_init_asp(&dm365_evm_snd_data);
604 #elif defined(CONFIG_SND_DM365_VOICE_CODEC)
605 dm365_init_vc(&dm365_evm_snd_data);
608 dm365_init_ks(&dm365evm_ks_data);
610 dm365_init_spi0(BIT(0), dm365_evm_spi_info,
611 ARRAY_SIZE(dm365_evm_spi_info));
614 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
615 .atag_offset = 0x100,
616 .map_io = dm365_evm_map_io,
617 .init_irq = davinci_irq_init,
618 .timer = &davinci_timer,
619 .init_machine = dm365_evm_init,
620 .dma_zone_size = SZ_128M,