arch/arm/mach-at91/setup.c

   1 /*
   2  * Copyright (C) 2007 Atmel Corporation.
   3  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   4  *
   5  * Under GPLv2
   6  */
   7
   8 #define pr_fmt(fmt)     "AT91: " fmt
   9
  10 #include <linux/module.h>
  11 #include <linux/io.h>
  12 #include <linux/mm.h>
  13 #include <linux/pm.h>
  14 #include <linux/of_address.h>
  15 #include <linux/pinctrl/machine.h>
  16 #include <linux/clk/at91_pmc.h>
  17
  18 #include <asm/system_misc.h>
  19 #include <asm/mach/map.h>
  20
  21 #include <mach/hardware.h>
  22 #include <mach/cpu.h>
  23 #include <mach/at91_dbgu.h>
  24
  25 #include "generic.h"
  26 #include "pm.h"
  27
  28 struct at91_socinfo at91_soc_initdata;
  29 EXPORT_SYMBOL(at91_soc_initdata);
  30
  31 void __iomem *at91_ramc_base[2];
  32 EXPORT_SYMBOL_GPL(at91_ramc_base);
  33
  34 static struct map_desc at91_io_desc __initdata __maybe_unused = {
  35         .virtual        = (unsigned long)AT91_VA_BASE_SYS,
  36         .pfn            = __phys_to_pfn(AT91_BASE_SYS),
  37         .length         = SZ_16K,
  38         .type           = MT_DEVICE,
  39 };
  40
  41 static struct map_desc at91_alt_io_desc __initdata __maybe_unused = {
  42         .virtual        = (unsigned long)AT91_ALT_VA_BASE_SYS,
  43         .pfn            = __phys_to_pfn(AT91_ALT_BASE_SYS),
  44         .length         = 24 * SZ_1K,
  45         .type           = MT_DEVICE,
  46 };
  47
  48 static void __init soc_detect(u32 dbgu_base)
  49 {
  50         u32 cidr, socid;
  51
  52         cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
  53         socid = cidr & ~AT91_CIDR_VERSION;
  54
  55         switch (socid) {
  56         case ARCH_ID_AT91RM9200:
  57                 at91_soc_initdata.type = AT91_SOC_RM9200;
  58                 if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN)
  59                         at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
  60                 break;
  61
  62         case ARCH_ID_AT91SAM9260:
  63                 at91_soc_initdata.type = AT91_SOC_SAM9260;
  64                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  65                 break;
  66
  67         case ARCH_ID_AT91SAM9261:
  68                 at91_soc_initdata.type = AT91_SOC_SAM9261;
  69                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  70                 break;
  71
  72         case ARCH_ID_AT91SAM9263:
  73                 at91_soc_initdata.type = AT91_SOC_SAM9263;
  74                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  75                 break;
  76
  77         case ARCH_ID_AT91SAM9G20:
  78                 at91_soc_initdata.type = AT91_SOC_SAM9G20;
  79                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  80                 break;
  81
  82         case ARCH_ID_AT91SAM9G45:
  83                 at91_soc_initdata.type = AT91_SOC_SAM9G45;
  84                 if (cidr == ARCH_ID_AT91SAM9G45ES)
  85                         at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
  86                 break;
  87
  88         case ARCH_ID_AT91SAM9RL64:
  89                 at91_soc_initdata.type = AT91_SOC_SAM9RL;
  90                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  91                 break;
  92
  93         case ARCH_ID_AT91SAM9X5:
  94                 at91_soc_initdata.type = AT91_SOC_SAM9X5;
  95                 break;
  96
  97         case ARCH_ID_AT91SAM9N12:
  98                 at91_soc_initdata.type = AT91_SOC_SAM9N12;
  99                 break;
 100
 101         case ARCH_ID_SAMA5:
 102                 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 103                 if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
 104                         at91_soc_initdata.type = AT91_SOC_SAMA5D3;
 105                 }
 106                 break;
 107         }
 108
 109         /* at91sam9g10 */
 110         if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
 111                 at91_soc_initdata.type = AT91_SOC_SAM9G10;
 112                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 113         }
 114         /* at91sam9xe */
 115         else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
 116                 at91_soc_initdata.type = AT91_SOC_SAM9260;
 117                 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
 118         }
 119
 120         if (!at91_soc_is_detected())
 121                 return;
 122
 123         at91_soc_initdata.cidr = cidr;
 124
 125         /* sub version of soc */
 126         if (!at91_soc_initdata.exid)
 127                 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 128
 129         if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
 130                 switch (at91_soc_initdata.exid) {
 131                 case ARCH_EXID_AT91SAM9M10:
 132                         at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
 133                         break;
 134                 case ARCH_EXID_AT91SAM9G46:
 135                         at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
 136                         break;
 137                 case ARCH_EXID_AT91SAM9M11:
 138                         at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
 139                         break;
 140                 }
 141         }
 142
 143         if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
 144                 switch (at91_soc_initdata.exid) {
 145                 case ARCH_EXID_AT91SAM9G15:
 146                         at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
 147                         break;
 148                 case ARCH_EXID_AT91SAM9G35:
 149                         at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
 150                         break;
 151                 case ARCH_EXID_AT91SAM9X35:
 152                         at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
 153                         break;
 154                 case ARCH_EXID_AT91SAM9G25:
 155                         at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
 156                         break;
 157                 case ARCH_EXID_AT91SAM9X25:
 158                         at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
 159                         break;
 160                 }
 161         }
 162
 163         if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
 164                 switch (at91_soc_initdata.exid) {
 165                 case ARCH_EXID_SAMA5D31:
 166                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
 167                         break;
 168                 case ARCH_EXID_SAMA5D33:
 169                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
 170                         break;
 171                 case ARCH_EXID_SAMA5D34:
 172                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
 173                         break;
 174                 case ARCH_EXID_SAMA5D35:
 175                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
 176                         break;
 177                 case ARCH_EXID_SAMA5D36:
 178                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D36;
 179                         break;
 180                 }
 181         }
 182 }
 183
 184 static void __init alt_soc_detect(u32 dbgu_base)
 185 {
 186         u32 cidr, socid;
 187
 188         /* SoC ID */
 189         cidr = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
 190         socid = cidr & ~AT91_CIDR_VERSION;
 191
 192         switch (socid) {
 193         case ARCH_ID_SAMA5:
 194                 at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 195                 if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
 196                         at91_soc_initdata.type = AT91_SOC_SAMA5D3;
 197                 } else if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D4) {
 198                         at91_soc_initdata.type = AT91_SOC_SAMA5D4;
 199                 }
 200                 break;
 201         }
 202
 203         if (!at91_soc_is_detected())
 204                 return;
 205
 206         at91_soc_initdata.cidr = cidr;
 207
 208         /* sub version of soc */
 209         if (!at91_soc_initdata.exid)
 210                 at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 211
 212         if (at91_soc_initdata.type == AT91_SOC_SAMA5D4) {
 213                 switch (at91_soc_initdata.exid) {
 214                 case ARCH_EXID_SAMA5D41:
 215                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D41;
 216                         break;
 217                 case ARCH_EXID_SAMA5D42:
 218                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D42;
 219                         break;
 220                 case ARCH_EXID_SAMA5D43:
 221                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D43;
 222                         break;
 223                 case ARCH_EXID_SAMA5D44:
 224                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D44;
 225                         break;
 226                 }
 227         }
 228 }
 229
 230 static const char *soc_name[] = {
 231         [AT91_SOC_RM9200]       = "at91rm9200",
 232         [AT91_SOC_SAM9260]      = "at91sam9260",
 233         [AT91_SOC_SAM9261]      = "at91sam9261",
 234         [AT91_SOC_SAM9263]      = "at91sam9263",
 235         [AT91_SOC_SAM9G10]      = "at91sam9g10",
 236         [AT91_SOC_SAM9G20]      = "at91sam9g20",
 237         [AT91_SOC_SAM9G45]      = "at91sam9g45",
 238         [AT91_SOC_SAM9RL]       = "at91sam9rl",
 239         [AT91_SOC_SAM9X5]       = "at91sam9x5",
 240         [AT91_SOC_SAM9N12]      = "at91sam9n12",
 241         [AT91_SOC_SAMA5D3]      = "sama5d3",
 242         [AT91_SOC_SAMA5D4]      = "sama5d4",
 243         [AT91_SOC_UNKNOWN]      = "Unknown",
 244 };
 245
 246 const char *at91_get_soc_type(struct at91_socinfo *c)
 247 {
 248         return soc_name[c->type];
 249 }
 250 EXPORT_SYMBOL(at91_get_soc_type);
 251
 252 static const char *soc_subtype_name[] = {
 253         [AT91_SOC_RM9200_BGA]   = "at91rm9200 BGA",
 254         [AT91_SOC_RM9200_PQFP]  = "at91rm9200 PQFP",
 255         [AT91_SOC_SAM9XE]       = "at91sam9xe",
 256         [AT91_SOC_SAM9G45ES]    = "at91sam9g45es",
 257         [AT91_SOC_SAM9M10]      = "at91sam9m10",
 258         [AT91_SOC_SAM9G46]      = "at91sam9g46",
 259         [AT91_SOC_SAM9M11]      = "at91sam9m11",
 260         [AT91_SOC_SAM9G15]      = "at91sam9g15",
 261         [AT91_SOC_SAM9G35]      = "at91sam9g35",
 262         [AT91_SOC_SAM9X35]      = "at91sam9x35",
 263         [AT91_SOC_SAM9G25]      = "at91sam9g25",
 264         [AT91_SOC_SAM9X25]      = "at91sam9x25",
 265         [AT91_SOC_SAMA5D31]     = "sama5d31",
 266         [AT91_SOC_SAMA5D33]     = "sama5d33",
 267         [AT91_SOC_SAMA5D34]     = "sama5d34",
 268         [AT91_SOC_SAMA5D35]     = "sama5d35",
 269         [AT91_SOC_SAMA5D36]     = "sama5d36",
 270         [AT91_SOC_SAMA5D41]     = "sama5d41",
 271         [AT91_SOC_SAMA5D42]     = "sama5d42",
 272         [AT91_SOC_SAMA5D43]     = "sama5d43",
 273         [AT91_SOC_SAMA5D44]     = "sama5d44",
 274         [AT91_SOC_SUBTYPE_NONE] = "None",
 275         [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
 276 };
 277
 278 const char *at91_get_soc_subtype(struct at91_socinfo *c)
 279 {
 280         return soc_subtype_name[c->subtype];
 281 }
 282 EXPORT_SYMBOL(at91_get_soc_subtype);
 283
 284 void __init at91_map_io(void)
 285 {
 286         /* Map peripherals */
 287         iotable_init(&at91_io_desc, 1);
 288
 289         at91_soc_initdata.type = AT91_SOC_UNKNOWN;
 290         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
 291
 292         soc_detect(AT91_BASE_DBGU0);
 293         if (!at91_soc_is_detected())
 294                 soc_detect(AT91_BASE_DBGU1);
 295
 296         if (!at91_soc_is_detected())
 297                 panic(pr_fmt("Impossible to detect the SOC type"));
 298
 299         pr_info("Detected soc type: %s\n",
 300                 at91_get_soc_type(&at91_soc_initdata));
 301         if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
 302                 pr_info("Detected soc subtype: %s\n",
 303                         at91_get_soc_subtype(&at91_soc_initdata));
 304 }
 305
 306 void __init at91_alt_map_io(void)
 307 {
 308         /* Map peripherals */
 309         iotable_init(&at91_alt_io_desc, 1);
 310
 311         at91_soc_initdata.type = AT91_SOC_UNKNOWN;
 312         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
 313
 314         alt_soc_detect(AT91_BASE_DBGU2);
 315         if (!at91_soc_is_detected())
 316                 panic("AT91: Impossible to detect the SOC type");
 317
 318         pr_info("AT91: Detected soc type: %s\n",
 319                 at91_get_soc_type(&at91_soc_initdata));
 320         if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
 321                 pr_info("AT91: Detected soc subtype: %s\n",
 322                         at91_get_soc_subtype(&at91_soc_initdata));
 323 }
 324
 325 void __iomem *at91_matrix_base;
 326 EXPORT_SYMBOL_GPL(at91_matrix_base);
 327
 328 void __init at91_ioremap_matrix(u32 base_addr)
 329 {
 330         at91_matrix_base = ioremap(base_addr, 512);
 331         if (!at91_matrix_base)
 332                 panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
 333 }
 334
 335 static struct of_device_id ramc_ids[] = {
 336         { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
 337         { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
 338         { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
 339         { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
 340         { /*sentinel*/ }
 341 };
 342
 343 static void at91_dt_ramc(void)
 344 {
 345         struct device_node *np;
 346         const struct of_device_id *of_id;
 347         int idx = 0;
 348         const void *standby = NULL;
 349
 350         for_each_matching_node_and_match(np, ramc_ids, &of_id) {
 351                 at91_ramc_base[idx] = of_iomap(np, 0);
 352                 if (!at91_ramc_base[idx])
 353                         panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
 354
 355                 if (!standby)
 356                         standby = of_id->data;
 357
 358                 idx++;
 359         }
 360
 361         if (!idx)
 362                 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
 363
 364         if (!standby) {
 365                 pr_warn("ramc no standby function available\n");
 366                 return;
 367         }
 368
 369         at91_pm_set_standby(standby);
 370 }
 371
 372 void __init at91_dt_initialize(void)
 373 {
 374         at91_dt_ramc();
 375 }