arch/arm/mach-at91/setup.c

   1 /*
   2  * Copyright (C) 2007 Atmel Corporation.
   3  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   4  *
   5  * Under GPLv2
   6  */
   7
   8 #define pr_fmt(fmt)     "AT91: " fmt
   9
  10 #include <linux/module.h>
  11 #include <linux/io.h>
  12 #include <linux/mm.h>
  13 #include <linux/pm.h>
  14 #include <linux/of_address.h>
  15 #include <linux/pinctrl/machine.h>
  16 #include <linux/clk/at91_pmc.h>
  17
  18 #include <asm/system_misc.h>
  19 #include <asm/mach/map.h>
  20
  21 #include <mach/hardware.h>
  22 #include <mach/cpu.h>
  23 #include <mach/at91_dbgu.h>
  24
  25 #include "soc.h"
  26 #include "generic.h"
  27 #include "pm.h"
  28
  29 struct at91_init_soc __initdata at91_boot_soc;
  30
  31 struct at91_socinfo at91_soc_initdata;
  32 EXPORT_SYMBOL(at91_soc_initdata);
  33
  34 void __iomem *at91_ramc_base[2];
  35 EXPORT_SYMBOL_GPL(at91_ramc_base);
  36
  37 static struct map_desc sram_desc[2] __initdata;
  38
  39 void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
  40 {
  41         struct map_desc *desc = &sram_desc[bank];
  42
  43         desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
  44         if (bank > 0)
  45                 desc->virtual -= sram_desc[bank - 1].length;
  46
  47         desc->pfn = __phys_to_pfn(base);
  48         desc->length = length;
  49         desc->type = MT_MEMORY_RWX_NONCACHED;
  50
  51         pr_info("sram at 0x%lx of 0x%x mapped at 0x%lx\n",
  52                 base, length, desc->virtual);
  53
  54         iotable_init(desc, 1);
  55 }
  56
  57 static struct map_desc at91_io_desc __initdata __maybe_unused = {
  58         .virtual        = (unsigned long)AT91_VA_BASE_SYS,
  59         .pfn            = __phys_to_pfn(AT91_BASE_SYS),
  60         .length         = SZ_16K,
  61         .type           = MT_DEVICE,
  62 };
  63
  64 static struct map_desc at91_alt_io_desc __initdata __maybe_unused = {
  65         .virtual        = (unsigned long)AT91_ALT_VA_BASE_SYS,
  66         .pfn            = __phys_to_pfn(AT91_ALT_BASE_SYS),
  67         .length         = 24 * SZ_1K,
  68         .type           = MT_DEVICE,
  69 };
  70
  71 static void __init soc_detect(u32 dbgu_base)
  72 {
  73         u32 cidr, socid;
  74
  75         cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
  76         socid = cidr & ~AT91_CIDR_VERSION;
  77
  78         switch (socid) {
  79         case ARCH_ID_AT91RM9200:
  80                 at91_soc_initdata.type = AT91_SOC_RM9200;
  81                 if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN)
  82                         at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
  83                 at91_boot_soc = at91rm9200_soc;
  84                 break;
  85
  86         case ARCH_ID_AT91SAM9260:
  87                 at91_soc_initdata.type = AT91_SOC_SAM9260;
  88                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  89                 at91_boot_soc = at91sam9260_soc;
  90                 break;
  91
  92         case ARCH_ID_AT91SAM9261:
  93                 at91_soc_initdata.type = AT91_SOC_SAM9261;
  94                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  95                 at91_boot_soc = at91sam9261_soc;
  96                 break;
  97
  98         case ARCH_ID_AT91SAM9263:
  99                 at91_soc_initdata.type = AT91_SOC_SAM9263;
 100                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 101                 at91_boot_soc = at91sam9263_soc;
 102                 break;
 103
 104         case ARCH_ID_AT91SAM9G20:
 105                 at91_soc_initdata.type = AT91_SOC_SAM9G20;
 106                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 107                 at91_boot_soc = at91sam9260_soc;
 108                 break;
 109
 110         case ARCH_ID_AT91SAM9G45:
 111                 at91_soc_initdata.type = AT91_SOC_SAM9G45;
 112                 if (cidr == ARCH_ID_AT91SAM9G45ES)
 113                         at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
 114                 at91_boot_soc = at91sam9g45_soc;
 115                 break;
 116
 117         case ARCH_ID_AT91SAM9RL64:
 118                 at91_soc_initdata.type = AT91_SOC_SAM9RL;
 119                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 120                 at91_boot_soc = at91sam9rl_soc;
 121                 break;
 122
 123         case ARCH_ID_AT91SAM9X5:
 124                 at91_soc_initdata.type = AT91_SOC_SAM9X5;
 125                 at91_boot_soc = at91sam9x5_soc;
 126                 break;
 127
 128         case ARCH_ID_AT91SAM9N12:
 129                 at91_soc_initdata.type = AT91_SOC_SAM9N12;
 130                 at91_boot_soc = at91sam9n12_soc;
 131                 break;
 132
 133         case ARCH_ID_SAMA5:
 134                 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 135                 if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
 136                         at91_soc_initdata.type = AT91_SOC_SAMA5D3;
 137                         at91_boot_soc = sama5d3_soc;
 138                 }
 139                 break;
 140         }
 141
 142         /* at91sam9g10 */
 143         if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
 144                 at91_soc_initdata.type = AT91_SOC_SAM9G10;
 145                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 146                 at91_boot_soc = at91sam9261_soc;
 147         }
 148         /* at91sam9xe */
 149         else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
 150                 at91_soc_initdata.type = AT91_SOC_SAM9260;
 151                 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
 152                 at91_boot_soc = at91sam9260_soc;
 153         }
 154
 155         if (!at91_soc_is_detected())
 156                 return;
 157
 158         at91_soc_initdata.cidr = cidr;
 159
 160         /* sub version of soc */
 161         if (!at91_soc_initdata.exid)
 162                 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 163
 164         if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
 165                 switch (at91_soc_initdata.exid) {
 166                 case ARCH_EXID_AT91SAM9M10:
 167                         at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
 168                         break;
 169                 case ARCH_EXID_AT91SAM9G46:
 170                         at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
 171                         break;
 172                 case ARCH_EXID_AT91SAM9M11:
 173                         at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
 174                         break;
 175                 }
 176         }
 177
 178         if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
 179                 switch (at91_soc_initdata.exid) {
 180                 case ARCH_EXID_AT91SAM9G15:
 181                         at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
 182                         break;
 183                 case ARCH_EXID_AT91SAM9G35:
 184                         at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
 185                         break;
 186                 case ARCH_EXID_AT91SAM9X35:
 187                         at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
 188                         break;
 189                 case ARCH_EXID_AT91SAM9G25:
 190                         at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
 191                         break;
 192                 case ARCH_EXID_AT91SAM9X25:
 193                         at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
 194                         break;
 195                 }
 196         }
 197
 198         if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
 199                 switch (at91_soc_initdata.exid) {
 200                 case ARCH_EXID_SAMA5D31:
 201                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
 202                         break;
 203                 case ARCH_EXID_SAMA5D33:
 204                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
 205                         break;
 206                 case ARCH_EXID_SAMA5D34:
 207                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
 208                         break;
 209                 case ARCH_EXID_SAMA5D35:
 210                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
 211                         break;
 212                 case ARCH_EXID_SAMA5D36:
 213                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D36;
 214                         break;
 215                 }
 216         }
 217 }
 218
 219 static void __init alt_soc_detect(u32 dbgu_base)
 220 {
 221         u32 cidr, socid;
 222
 223         /* SoC ID */
 224         cidr = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
 225         socid = cidr & ~AT91_CIDR_VERSION;
 226
 227         switch (socid) {
 228         case ARCH_ID_SAMA5:
 229                 at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 230                 if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
 231                         at91_soc_initdata.type = AT91_SOC_SAMA5D3;
 232                         at91_boot_soc = sama5d3_soc;
 233                 } else if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D4) {
 234                         at91_soc_initdata.type = AT91_SOC_SAMA5D4;
 235                         at91_boot_soc = sama5d4_soc;
 236                 }
 237                 break;
 238         }
 239
 240         if (!at91_soc_is_detected())
 241                 return;
 242
 243         at91_soc_initdata.cidr = cidr;
 244
 245         /* sub version of soc */
 246         if (!at91_soc_initdata.exid)
 247                 at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 248
 249         if (at91_soc_initdata.type == AT91_SOC_SAMA5D4) {
 250                 switch (at91_soc_initdata.exid) {
 251                 case ARCH_EXID_SAMA5D41:
 252                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D41;
 253                         break;
 254                 case ARCH_EXID_SAMA5D42:
 255                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D42;
 256                         break;
 257                 case ARCH_EXID_SAMA5D43:
 258                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D43;
 259                         break;
 260                 case ARCH_EXID_SAMA5D44:
 261                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D44;
 262                         break;
 263                 }
 264         }
 265 }
 266
 267 static const char *soc_name[] = {
 268         [AT91_SOC_RM9200]       = "at91rm9200",
 269         [AT91_SOC_SAM9260]      = "at91sam9260",
 270         [AT91_SOC_SAM9261]      = "at91sam9261",
 271         [AT91_SOC_SAM9263]      = "at91sam9263",
 272         [AT91_SOC_SAM9G10]      = "at91sam9g10",
 273         [AT91_SOC_SAM9G20]      = "at91sam9g20",
 274         [AT91_SOC_SAM9G45]      = "at91sam9g45",
 275         [AT91_SOC_SAM9RL]       = "at91sam9rl",
 276         [AT91_SOC_SAM9X5]       = "at91sam9x5",
 277         [AT91_SOC_SAM9N12]      = "at91sam9n12",
 278         [AT91_SOC_SAMA5D3]      = "sama5d3",
 279         [AT91_SOC_SAMA5D4]      = "sama5d4",
 280         [AT91_SOC_UNKNOWN]      = "Unknown",
 281 };
 282
 283 const char *at91_get_soc_type(struct at91_socinfo *c)
 284 {
 285         return soc_name[c->type];
 286 }
 287 EXPORT_SYMBOL(at91_get_soc_type);
 288
 289 static const char *soc_subtype_name[] = {
 290         [AT91_SOC_RM9200_BGA]   = "at91rm9200 BGA",
 291         [AT91_SOC_RM9200_PQFP]  = "at91rm9200 PQFP",
 292         [AT91_SOC_SAM9XE]       = "at91sam9xe",
 293         [AT91_SOC_SAM9G45ES]    = "at91sam9g45es",
 294         [AT91_SOC_SAM9M10]      = "at91sam9m10",
 295         [AT91_SOC_SAM9G46]      = "at91sam9g46",
 296         [AT91_SOC_SAM9M11]      = "at91sam9m11",
 297         [AT91_SOC_SAM9G15]      = "at91sam9g15",
 298         [AT91_SOC_SAM9G35]      = "at91sam9g35",
 299         [AT91_SOC_SAM9X35]      = "at91sam9x35",
 300         [AT91_SOC_SAM9G25]      = "at91sam9g25",
 301         [AT91_SOC_SAM9X25]      = "at91sam9x25",
 302         [AT91_SOC_SAMA5D31]     = "sama5d31",
 303         [AT91_SOC_SAMA5D33]     = "sama5d33",
 304         [AT91_SOC_SAMA5D34]     = "sama5d34",
 305         [AT91_SOC_SAMA5D35]     = "sama5d35",
 306         [AT91_SOC_SAMA5D36]     = "sama5d36",
 307         [AT91_SOC_SAMA5D41]     = "sama5d41",
 308         [AT91_SOC_SAMA5D42]     = "sama5d42",
 309         [AT91_SOC_SAMA5D43]     = "sama5d43",
 310         [AT91_SOC_SAMA5D44]     = "sama5d44",
 311         [AT91_SOC_SUBTYPE_NONE] = "None",
 312         [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
 313 };
 314
 315 const char *at91_get_soc_subtype(struct at91_socinfo *c)
 316 {
 317         return soc_subtype_name[c->subtype];
 318 }
 319 EXPORT_SYMBOL(at91_get_soc_subtype);
 320
 321 void __init at91_map_io(void)
 322 {
 323         /* Map peripherals */
 324         iotable_init(&at91_io_desc, 1);
 325
 326         at91_soc_initdata.type = AT91_SOC_UNKNOWN;
 327         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
 328
 329         soc_detect(AT91_BASE_DBGU0);
 330         if (!at91_soc_is_detected())
 331                 soc_detect(AT91_BASE_DBGU1);
 332
 333         if (!at91_soc_is_detected())
 334                 panic(pr_fmt("Impossible to detect the SOC type"));
 335
 336         pr_info("Detected soc type: %s\n",
 337                 at91_get_soc_type(&at91_soc_initdata));
 338         if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
 339                 pr_info("Detected soc subtype: %s\n",
 340                         at91_get_soc_subtype(&at91_soc_initdata));
 341
 342         if (!at91_soc_is_enabled())
 343                 panic(pr_fmt("Soc not enabled"));
 344
 345         if (at91_boot_soc.map_io)
 346                 at91_boot_soc.map_io();
 347 }
 348
 349 void __init at91_alt_map_io(void)
 350 {
 351         /* Map peripherals */
 352         iotable_init(&at91_alt_io_desc, 1);
 353
 354         at91_soc_initdata.type = AT91_SOC_UNKNOWN;
 355         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
 356
 357         alt_soc_detect(AT91_BASE_DBGU2);
 358         if (!at91_soc_is_detected())
 359                 panic("AT91: Impossible to detect the SOC type");
 360
 361         pr_info("AT91: Detected soc type: %s\n",
 362                 at91_get_soc_type(&at91_soc_initdata));
 363         if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
 364                 pr_info("AT91: Detected soc subtype: %s\n",
 365                         at91_get_soc_subtype(&at91_soc_initdata));
 366
 367         if (!at91_soc_is_enabled())
 368                 panic("AT91: Soc not enabled");
 369
 370         if (at91_boot_soc.map_io)
 371                 at91_boot_soc.map_io();
 372 }
 373
 374 void __iomem *at91_matrix_base;
 375 EXPORT_SYMBOL_GPL(at91_matrix_base);
 376
 377 void __init at91_ioremap_matrix(u32 base_addr)
 378 {
 379         at91_matrix_base = ioremap(base_addr, 512);
 380         if (!at91_matrix_base)
 381                 panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
 382 }
 383
 384 static struct of_device_id ramc_ids[] = {
 385         { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
 386         { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
 387         { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
 388         { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
 389         { /*sentinel*/ }
 390 };
 391
 392 static void at91_dt_ramc(void)
 393 {
 394         struct device_node *np;
 395         const struct of_device_id *of_id;
 396         int idx = 0;
 397         const void *standby = NULL;
 398
 399         for_each_matching_node_and_match(np, ramc_ids, &of_id) {
 400                 at91_ramc_base[idx] = of_iomap(np, 0);
 401                 if (!at91_ramc_base[idx])
 402                         panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
 403
 404                 if (!standby)
 405                         standby = of_id->data;
 406
 407                 idx++;
 408         }
 409
 410         if (!idx)
 411                 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
 412
 413         if (!standby) {
 414                 pr_warn("ramc no standby function available\n");
 415                 return;
 416         }
 417
 418         at91_pm_set_standby(standby);
 419 }
 420
 421 void __init at91_dt_initialize(void)
 422 {
 423         at91_dt_ramc();
 424
 425         if (at91_boot_soc.init)
 426                 at91_boot_soc.init();
 427 }